Project 01 — RTL pass on the first try

Wrote the 4-bit ALU plus an exhaustive testbench. 1024/1024 vectors match the reference model on the first compile.

Icarus did warn that top.v has no \timescale` — that’s deliberate. Putting timescale in design modules locks them to a particular sim scale; the testbench is where time lives. The warning is informational and the right answer is to ignore it.

What’s in src/top.v

• One module, all combinational, all assign.
• A 5-bit sum5 so the add op has a real carry-out bit (sum5[4]).
• A nested ternary picks the op result. Could’ve been a case inside always @*; the project’s “next mutation #1” is to do exactly that and compare cell counts after harden.

What’s in test/tb.v

• Three nested for loops walking op × a × b.
• Inline reference model (no Python golden — kept it pure Verilog so this project doesn’t drag in a Python dep yet).
• Settles each vector with #1 before sampling DUT outputs. For pure combinational that’s overkill, but it’s the right habit; later projects with real flops will need it.

Pre-emptive worry

Project 01 deliberately has no clock. The LibreLane flow may not be happy about that. Set RUN_CTS: false and omit CLOCK_PORT in the config; if the floorplan/STA stages fall over anyway, the documented fallback is to wrap the ALU with a single output register and harden the wrapper.

That’s a problem for next session.

Where we are now

Repo is on master at gitlab.daringbit.com:josh/librelane-playground, GitLab CI builds the Astro site and deploys to Pages on master. LibreLane is not yet installed — that’s the next step. The Nix-based install is the recommended path per 00_environment/TOOLCHAIN_REPORT.md.

Toolchain that’s already on this box: nix, docker, yosys 0.16, iverilog 13, python3, make. Not yet installed: verilator, gtkwave, klayout, openroad, magic, netgen, RISC-V toolchain. LibreLane’s Nix flake should pull most of those.