librelane playground

section 04 work log

What happened, in order

One entry per working session, newest first. Dead ends, failed runs, toolchain bugs, design choices — all worth recording. The project pages are the polished writeups; this is the messy log behind them.

159 entries
137 projects touched
  1. 2026-05-07 2 entries
    1. Strict execute-prefetch guard 147_strict_execute_prefetch_guard
    2. Execute-prefetch predicate audit 146_execute_prefetch_predicate_audit
  2. 2026-05-06 41 entries
    1. P110 tagged auxiliary response 110_tagged_aux_response
    2. P117 - speculative target buffer guardrail 117_speculative_target_buffer
    3. P125 - Source-ready scoreboard model 125_source_ready_scoreboard
    4. P124 - Shadow integer issue slot 124_shadow_issue_slot
    5. P142: prefetch can deserve the second repair word too 142_selective_prefetch_second_word_repair
    6. P127: scheduler wakeup/issue eligibility 127_scheduler_wakeup_issue
    7. P128: scheduler queue/lifetime depth 128_scheduler_queue_lifetime
    8. P129: scheduler arrival/service decoupling 129_scheduler_arrival_service
    9. P121 - ROB commit model 121_rob_commit_model
    10. P140: one-word repair is better, but too stingy 140_repair_aware_icache_arbitration
    11. P130 - Ready/valid contract extraction 130_ready_valid_contract
    12. P114 PTW aux owner 114_ptw_aux_owner
    13. P120 - PRF rename sketch 120_prf_rename_sketch
    14. P143: the prefetch repair bucket splits open 143_prefetch_consumer_repair_classifier
    15. P111 nonblocking load aux 111_nonblocking_load_aux
    16. P122 - Multi-entry ROB sketch 122_multi_entry_rob_sketch
    17. P126: memory/control holding records 126_memory_control_holding_records
    18. P118 - LSU shape counters 118_lsu_shape
    19. P119 - LSU request scoreboard 119_lsu_request_scoreboard
    20. P113 load miss policy 113_load_miss_policy
    21. P139: repair is fair, not necessarily useful 139_icache_repair_usefulness
    22. P136: I-cache background preemption is too aggressive 136_icache_background_preempt
    23. Frontend target queue 115_frontend_target_queue
    24. P144: throttling the noisy prefetch repair class 144_execute_prefetch_repair_throttle
    25. P131 - Dispatch queue module extraction 131_dispatch_queue_module
    26. P132 - Dispatch payload record 132_dispatch_payload_record
    27. P133 - Dispatch payload class audit 133_dispatch_payload_class_audit
    28. P123 - Dispatch/issue split sketch 123_dispatch_issue_split
    29. P138: debt beats the burst cap 138_debt_memory_arbitration
    30. Looking at OpenHW core-et (erbium), and the gap from here comparisonopenhwesperanto
    31. P145: conditional execute-prefetch repair 145_conditional_execute_prefetch_repair
    32. P135 - Cache background policy audit 135_cache_background_policy_audit
    33. P137: bounded I-cache preemption recovers P136 137_bounded_memory_arbitration
    34. Banked lower-memory contract 106_banked_lower_contract
    35. Banked auxiliary I-cache fill 108_banked_aux_icache_fill
    36. P109 banked aux demand prefetch 109_banked_aux_demand_fetch
    37. Banked auxiliary D-cache fill 107_banked_aux_dcache_fill
    38. P112 aux response queue 112_aux_response_queue
    39. P134 - Aux load prefetch policy 134_aux_load_prefetch_policy
    40. P141: demand lines deserve the second repair word 141_adaptive_second_word_icache_repair
    41. Active predictor steering 116_active_predictor_steering
  3. 2026-05-05 36 entries
    1. P102: the store buffer is not correct yet 102_write_buffer_forward linuxbusyboxstore-buffer
    2. P86 8-entry TLB shell perf 86_tlb_8entry_shell
    3. P83 TCC RV32 on chip 83_tcc_riscv32_on_chip
    4. Store-buffer trace repair 103_storebuf_trace_repair
    5. P95: store buffer v0 95_store_buffer
    6. P101: Split ITLB/DTLB 101_split_tlb
    7. P100: Split I/D service 100_split_id_service
    8. P84 shell profile flamegraph 84_shell_profile_flamegraph
    9. P78 AtomVM input IRQ mailbox bridge 78_atomvm_irq_mailbox
    10. P77 AtomVM input FIFO IRQ bridge 77_atomvm_input_irq
    11. P76 AtomVM batched input bridge 76_atomvm_event_source
    12. P75 AtomVM Tetris 75_atomvm_tetris
    13. P74 AtomVM interactive game host bridge 74_atomvm_interactive_game
    14. P73 AtomVM renders framebuffer frames 73_atomvm_framebuffer
    15. P72 AtomVM reaches chip-visible I/O 72_atomvm_chip_io
    16. P71 AtomVM stress - timers, workers, and allocation 71_atomvm_stress p71atomvmerlang
    17. P70 libc revival - newlib, FPU, and AtomVM ping-pong 70_f_libc p70libcnewlib
    18. Memory stall attribution for the BusyBox shell 88_memory_stall_attribution
    19. P94: memory arbiter v0 94_memory_arbiter
    20. Linux host TTY input 79_linux_host_tty
    21. Blocking I-cache line fill 90_icache_linefill
    22. P91 critical-word-first I-cache fill 91_icache_fill_buffer
    23. First tiny I-cache for fetch stalls 89_icache_fetch
    24. P99: Harvard I/D map 99_harvard_id_map
    25. P92: fetch queue 92_fetch_queue
    26. Direct UART console bridge 87_direct_uart_console
    27. P96: D-cache v0 96_dcache
    28. P98: D-cache throttle 98_dcache_throttle
    29. P97: D-cache line-fill 97_dcache_linefill
    30. P82 chip-side C compiler 82_chip_side_c_compiler
    31. P85 BusyBox symbol profile 85_busybox_symbol_profile
    32. BusyBox gets a real PTY 81_busybox_pty_console
    33. BusyBox initramfs start 80_busybox_initramfs
    34. P93: branch predictor v0 93_branch_predictor
    35. Banked lower service model 105_banked_lower_service
    36. Banked lower-memory conflict counters 104_banked_lower_memory
  4. 2026-05-04 4 entries
    1. P68 AtomVM port — bare-metal ELF links 68_atomvm_port p68atomvmbeam
    2. P68 AtomVM port — first implementation pass (scaffolding only) 68_atomvm_port p68atomvmbeam
    3. A repeatable benchmark suite for chip revisions 64_prefetch_under_wb benchfreertoslinux
    4. AtomVM research — can our chip run BEAM bytecode? 68_atomvm_port p68atomvmbeam
  5. 2026-05-03 21 entries
    1. Speed-push experiment on P37 37_rv32im_zicsr_zifencei p37librelanefmax
    2. P56 - the chip is ready for Linux 56_rtl_for_linux p56riscvsv32
    3. P55 - the chip runs a real S-mode kernel 55_hello_smode p55riscvsbi
    4. P54 - SBI shape works (the chip "boots a kernel" in miniature) 54_platform_shape p54riscvsbi
    5. P53 - filling the walker's gaps 53_walker_completion p53riscvsv32
    6. P52 - Sv32 paging works 52_sv32_walker p52riscvsv32
    7. P51 - priv-check on CSR access + the t1 clobber bug 51_csr_priv_check p51riscvpriv
    8. P50 - the chip takes its first trap in S-mode 50_smode_trap_routing p50riscvsmode
    9. P49 - cur_priv goes live 49_ms_priv_tracking p49riscvpriv
    10. P48 - trap delegation CSR scaffolding 48_trap_delegation_csrs p48riscvmdeleg
    11. P47 - S-mode CSR scaffolding 47_smode_csrs p47riscvsmode
    12. P46 - bitmanip but with a wart 46_zba_zbb p46riscvbitmanip
    13. P45 - atomics on the chip 45_a_extension p45riscvatomics
    14. P44 - the chip renders an animation 44_framebuffer_demo p44freertosframebuffer
    15. P43 fixes the halt sentinel and hardens FreeRTOS 43_freertos_hardened p43freertosmmio
    16. P42 boots a real FreeRTOS demo 42_freertos_demo p42freertosscheduler
    17. P41 lands the FreeRTOS port (compile) 41_freertos_port p41freertosport
    18. P40 audits the M-mode runtime 40_mmode_runtime_audit p40riscvruntime
    19. P39 lands Zicntr counters 39_zicntr_counters p39riscvzicntr
    20. P38 cleans up the arch-test plumbing 38_arch_test_official p38riscvarch-test
    21. Linux boots on the chip 59_ifetch_translation
  6. 2026-05-02 3 entries
    1. P37 closes Zicsr and Zifencei 37_rv32im_zicsr_zifencei p37riscvzicsr
    2. P36 clears the last fanout count 36_rv32im_divider_sign_stage p36rv32imharden
    3. P36 gets the first compliance gap sweep 36_rv32im_divider_sign_stage p36riscvcompliance
  7. 2026-05-01 16 entries
    1. Site accuracy audit after the ACT4 milestone siteauditriscv
    2. P36 clears the divider slew/cap tail 36_rv32im_divider_sign_stage p36riscvrv32m
    3. P35 makes fanout clean, not slew clean 35_rv32im_signoff_clean p35riscvrv32m
    4. P34 turns the DRV mess into a small tail 34_rv32im_drv_cleanup p34riscvrv32m
    5. P33 closes RV32IM setup timing 33_rv32im_timing_fix p33riscvrv32m
    6. P32 adds RV32M 32_rv32im_runtime_probe p32riscvrv32m
    7. P31 gets to freestanding C 31_rv32i_c_runtime_probe p31riscvruntime
    8. P30 adds a compiled tiny runtime 30_rv32i_tiny_runtime p30riscvruntime
    9. P29 moves the timer onto an MMIO map 29_rv32i_mmio_platform p29riscvmmio
    10. P28 adds timer and external interrupts 28_rv32i_machine_interrupts p28riscvinterrupts
    11. P27 adds the first machine-mode trap path 27_rv32i_machine_traps p27riscvcsr
    12. P27 hardens and keeps the ACT4 base-integer pass 27_rv32i_machine_traps p27riscvact4
    13. P26 makes the ACT4 probe repeatable 26_rv32i_act4_probe p26riscvcompliance
    14. P25 passes the local rv32i/I test set 25_rv32i_full_i_tests p25riscvcompliance
    15. P24 adds the official branch tests 24_rv32i_branch_tests p24riscvcompliance
    16. ACT4 generates RV32I/I ELFs that P17 can run 25_rv32i_full_i_tests p25riscvcompliance
  8. 2026-04-30 11 entries
    1. P23 adds the official JALR test 23_rv32i_jalr_tests p23riscvcompliance
    2. P22 adds the official JAL test 22_rv32i_jal_tests p22riscvcompliance
    3. P21 adds the official AUIPC test 21_rv32i_auipc_tests p21riscvcompliance
    4. P20 adds R-type ALU official tests 20_rv32i_rtype_alu_tests p20riscvcompliance
    5. P19 expands the official RV32I pass set 19_rv32i_imm_alu_tests p19riscvcompliance
    6. P18 gets LUI and ADDI past the official self-check 18_rv32i_lui_signature_debug p18riscvcompliance
    7. P17 hardens as a logic-only external-memory shell 17_rv32i_external_mem p17librelanehardening
    8. P17 turns memory skips into real arch-test failures 17_rv32i_external_mem p17riscvcompliance
    9. P16 loads the official smoke over UART 16_rv32i_sram_loader p16riscvsram
    10. P15 hardens as a bus-shell CPU 15_rv32i_arch_test p15librelaneriscv
    11. P15 gets the 8 KiB SRAM shape 15_rv32i_arch_test p15librelaneriscv
  9. 2026-04-29 7 entries
    1. P15 gets the first official RISC-V arch-test PASS 15_rv32i_arch_test p15riscvcompliance
    2. P14 official arch-test probe 14_rv32e_flash_boot p14riscvcompliance
    3. P14 — RV32E boots from SPI flash and hardens 14_rv32e_flash_boot p14hardenriscv
    4. P13 — RV32E + UART loader, hardened on a TT 8×2 tile 13_rv32e_loader p13hardenriscv
    5. P12 — RV32E hardened on a TT 8×2 tile 12_rv32e_tt p12hardenriscv
    6. P11 hardens the TT-wrapped P06 CPU 11_tt_cpu p11tinytapeoutcpu
    7. P10 TT wrapper hardens as a standalone sanity check 10_tiny_tapeout p10tinytapeoutlibrelane
  10. 2026-04-28 16 entries
    1. P11 — wrapping P06's CPU into the Tiny Tapeout pin frame 11_tt_cpu p11tinytapeoutwrapping
    2. P09 — C compiles to silicon 09_rv32i_min p09riscvtoolchain
    3. P09 — hardened, after a lesson in synth-side dead-code elimination 09_rv32i_min p09hardenyosys
    4. P10 — Tiny Tapeout port of the P02 counter/PWM/LFSR 10_tiny_tapeout p10
    5. P09 — RV32I-min, the first real ISA on the ladder 09_rv32i_min p09
    6. P08 — macro integration, bringing up a real OpenRAM SRAM 08_macro_integration p08
    7. P07 — tiny SoC, three hardens, lands at 71 MHz 07_tiny_soc p07harden
    8. Site infrastructure — Mermaid, /stack rebuild, real SV highlighting siteinfra
    9. P06 — the first CPU, plus a real UART hanging off it 06_fsm_cpu p06harden
    10. P05 — the ALU/datapath, hardened the third time at 40 MHz 05_alu_datapath p05harden
    11. Annotations grow up — line, chip-coord, and a glossary siteviewerinfra
    12. Project 03 RTL — UART transmitter 03_uart_tx project-03uartrtl
    13. Project 02 hardened — first flops, plus a viewer pipeline rebuild 02_counter_pwm_lfsr project-02librelaneharden
    14. Project 01 hardened — clean signoff on the first try 01_comb_logic project-01librelaneharden
    15. P08 macro integration hardens, with DRC caveats 08_macro_integration p08librelanemacro
    16. P03 and P04 hardened, four projects on the board 04_spi_gpio_peripheral project-03project-04hardened
  11. 2026-04-27 2 entries
    1. Project 01 — RTL pass on the first try 01_comb_logic project-01rtlsim
    2. Day zero — scaffolding metascaffold