This site is a learning notebook. The premise: I’ve never designed a chip before. I’d like to. There is a free toolchain called LibreLane that takes a description of a digital circuit and produces a fabrication-ready file for a real chip manufacturing process. We’re going to walk a ten-project ladder that ends, ten projects from now, with a tiny RISC-V CPU. This page is the orientation before we start.

What is a chip, physically?

A modern silicon chip is a flat piece of crystal silicon, usually somewhere between 1 mm and 30 mm on a side, with billions of microscopic structures patterned onto its surface. The structures are transistors — tiny switches — and the wires that connect them. Wires aren’t actually wires; they’re flat strips of metal a few hundred nanometers wide, stacked in layers above the transistor plane and connected vertically by little pillars called vias.

A chip is built one layer at a time, by exposing patterned light onto a wafer coated with photoreactive chemicals, then etching away or depositing material wherever the light landed. Each layer needs its own pattern (its own “mask”). The set of all masks for one chip is the chip’s GDS file (an industry-standard format named for “Graphic Database System”). Producing a clean, manufacturable GDS from a behavioral description of the circuit is the whole job of the EDA flow we’re using.

What is a transistor, what is a gate, what is a cell?

Three nested concepts:

A transistor is a switch. In digital logic it has one of two states (on / off), and the state is controlled by a voltage on its “gate” terminal. Transistors come in two flavors (NMOS and PMOS) and you wire them up in pairs to build logic.

A logic gate is a small circuit of a few transistors that implements one boolean operation: AND, OR, XOR, NAND, NOT, and so on. A 2-input NAND in CMOS is four transistors. An XOR is twelve. You don’t usually design them; somebody else did, in a foundry, decades ago, and the result is encoded in a standard cell library.

A standard cell is one prebuilt logic gate (or flip-flop, mux, buffer, etc.), packaged with a known footprint and electrical behavior. The library we’re using is sky130_fd_sc_hd — sky130’s “high-density” standard cell library, ~400 cells covering everything from basic gates to full-adders to D flip-flops. When you see “81 stdcells” in a project’s metrics, that’s how many of these prebuilt cells the flow placed on the die.

What is RTL? What is Verilog?

We don’t draw chips by hand. We describe them. The description language is called RTL (“register-transfer level”), and the most common specific dialect is Verilog. RTL is a programming language that compiles to gates instead of CPU instructions.

Here’s a 4-bit adder in Verilog:

module adder (
    input  wire [3:0] a, b,
    output wire [4:0] sum
);
  assign sum = {1'b0, a} + {1'b0, b};
endmodule

That’s a complete, synthesizable circuit description. A tool called Yosys reads this and produces a list of standard cells from sky130’s library wired together to perform that addition: probably four full-adder cells and a fifth half-adder for the carry-out. We did not draw the gates. We described the function and let synthesis find the gates.

RTL is “register-transfer level” because the canonical form describes how data moves between registers (flip-flops) on each clock edge. Project 01 has no registers — it’s pure combinational. Everything from project 02 onward will have registers, because that’s where digital design actually lives.

What does the EDA flow do?

EDA = “electronic design automation.” The software that turns RTL into a manufacturable chip. There are seven big phases. We’ll meet them in detail in project 01; here’s the one-paragraph overview:

Lint — read the RTL and complain about suspicious patterns (a typo’d signal, a forgotten branch in a case statement, a clock used as data).
Synthesis — translate RTL into a netlist of standard cells. Yosys’s job. Output: “instantiate this AND2, this NAND3, this DFF; connect their pins like so.”
Floorplan — decide the chip’s overall shape, where the IO pins go, where the power grid runs.
Placement — pick a specific (x, y) for every cell.
Clock tree synthesis (CTS) — build the wire network that distributes the clock signal everywhere it needs to go, with carefully balanced delays.
Routing — draw the actual metal wires that connect cell pins together, on metal layers 1 through 5.
Signoff — independent verification: timing analysis, DRC, LVS, antenna check.

All seven phases get done by separate tools coordinated by LibreLane. The phases produce a sequence of intermediate representations — Verilog netlist, DEF (placement), routed DEF, finally GDS — each one closer to silicon than the last.

What is sky130?

A PDK (“process design kit”) is the bundle of files that describes a specific manufacturing process. It tells the EDA tools: this is what a transistor looks like in our 130 nm process, here are the design rules (minimum metal width: 140 nm, minimum spacing between metal-2 wires: 140 nm, etc.), here is the standard cell library, here is the SPICE model for each device. PDKs used to be heavily NDA-protected — owning one was table stakes for any chip company.

sky130 is a PDK that SkyWater Technology open-sourced in 2020 in collaboration with Google. It’s a real 130 nm CMOS process — chips taped out against this PDK go to a real fab in Bloomington, Minnesota, and come back as actual silicon. The process is older (180 nm equivalent in some metrics) and modest by 2026 standards, but it’s the first time hobbyists and small teams could legally and freely design chips end-to-end.

“sky130A” in our metrics is the PDK variant we’re using. “sky130_fd_sc_hd” is sky130’s high-density standard cell library.

What is LibreLane?

LibreLane is the orchestration glue that runs the whole flow for you. It takes a config file pointing at your RTL and, behind the scenes, calls Yosys for synthesis, OpenROAD for placement and routing and timing, KLayout and Magic for DRC and GDS handling, Netgen for LVS, Verilator for lint, and a dozen smaller utilities for everything in between.

LibreLane is the rebranded successor to OpenLane (originally from Efabless). It’s all open source, runs on Linux/Mac, and we installed it on this box via Nix. When a project page on this site says “75 flow steps”, those are the 75 individual stages LibreLane sequenced for that hardening run.

Vocabulary cheat sheet

RTL: register-transfer level — the abstract behavioral description of a circuit, written in Verilog or VHDL. The thing you write.
HDL: hardware description language. Verilog and VHDL are HDLs. Often used interchangeably with “RTL”.
Netlist: a list of cells + the wires connecting them. The output of synthesis. Can be in Verilog format (“gate-level Verilog”) or LEF/DEF.
PDK: process design kit. The foundry’s package of design rules, cell libraries, and SPICE models for one specific manufacturing process.
Standard cell: a prebuilt small logic block (gate, flop, mux) from the PDK’s library. Comes with a fixed footprint and characterized timing.
GDS: Graphic Database System — the file format for the final chip layout. Has all the masks for all the layers. What gets sent to the fab.
LEF: library exchange format. Per-cell abstract footprint (just pins, blockages, dimensions) used during placement and routing.
DEF: design exchange format. The placed-and-routed design between flow stages.
DRC: design rule check. Geometric verification that the layout respects the PDK’s rules (minimum widths, spacings, enclosures).
LVS: layout vs schematic. Checks that the GDS, when interpreted as a circuit, matches the synthesized netlist device-for-device.
STA: static timing analysis. Computes worst-case delay through every signal path and checks it fits in one clock cycle.
Slack: the time margin between when a signal actually arrives and when it needed to arrive. Positive = you made it. Negative = you missed.
Antenna effect: charge build-up on long unconnected wires during fab can damage gate oxide. The antenna check finds these and the flow inserts diodes.
PVT corner: ”process, voltage, temperature” — combinations like “fast/slow silicon, high/low VDD, hot/cold”. Designs must meet timing at all PVT corners they’re rated for.
Tape-out: the moment you commit a GDS to the fab. Historic name from when designs were literally cut on tape.

Now what

Read the home page’s project ladder, then start with project 01. The project pages are written assuming you’ve read this page (so we don’t re-explain what RTL or DRC means every time), but they do explain everything project-specific.

A few principles for working through the ladder:

Read the run logs. Every project that hardens produces a runs/RUN_…/ directory packed with intermediate files. The interesting parts are final/metrics.csv, reports/synthesis/, and final/gds/. The first time you read a run dir it’s overwhelming; by project 03 you’ll know where to look.

Don’t trust your tools, verify them. The simulator says PASS — does the testbench actually exercise what you think? The flow says zero violations — but did you check that the right tools ran? Trusting metrics is a habit you build by first being burned by a metric that lied.

It’s okay if it doesn’t all click yet. You’ll see the same concepts (utilization, slack, drc, lvs) in five different projects. By the time we hit project 09 you’ll be bored of how predictable the harden output looks. That’s the goal.

→ Project 01: a 4-bit ALU