- project 01
Combinational logic playground
introduces gates, muxes, and what synthesis does when there is no clock to chase
- project 02
Counter, PWM, and LFSR
introduces flip-flops, clocks, real STA, the slow/fast clock-period experiment
- project 03
UART transmitter
introduces explicit FSM, baud generation, the first protocol, pin ordering
- project 04
SPI GPIO peripheral
introduces clock-domain crossing, two-FF synchronizers, memory-mapped registers, multi-edge pin placement
- project 05
Tiny ALU + datapath
introduces register file, flag register, 2R1W read ports, signed vs unsigned shifts
- project 06
Tiny FSM CPU
introduces program counter, instruction memory, instruction decode, multi-cycle FSM
- project 07
Tiny memory-mapped SoC
introduces bus, memory-mapped I/O, address decoder, UART RX
- project 08
Macro integration
introduces hard-IP integration, sync-read SRAM, sim-vs-synth model split
- project 09
RV32I-min educational CPU
introduces real ISA, 32-bit datapath, RISC-V instruction decode
- project 10
Tiny Tapeout port
introduces TT pin frame, fixed module signature, ena gating, uio bidirectional
- project 11
A real CPU on Tiny Tapeout
introduces TT shuttle architecture, user-mux, dev board, GHA submission flow
- project 12
RV32E for Tiny Tapeout
introduces RV32E, MMIO peripherals, TT 8×2 tile, observable-by-UART chip
- project 13
RV32E with a UART program loader
introduces writable instruction memory, UART RX, in-the-field reprogramming
- project 14
RV32E with SPI-flash boot
introduces SPI master, boot ROM controller, persistent program storage
- project 15
RV32I official arch-test smoke
introduces official RISC-V arch-test harness, self-check signatures, SRAM-backed memory bus
- project 16
RV32I SRAM UART loader
introduces UART-loaded SRAM boot path for the first official RV32I arch-test smoke
- project 17
RV32I external-memory arch-test runner
introduces Exposed memory bus for running larger official RV32I arch-test images
- project 18
RV32I official-test signature debug
introduces First non-trivial official RV32I instruction tests passing with generated self-check signatures
- project 19
RV32I immediate-ALU official subset
introduces Twelve official RV32I tests passing through generated signatures
- project 20
RV32I R-type ALU official subset
introduces Twenty-two official RV32I tests passing through generated signatures
- project 21
RV32I AUIPC official test
introduces AUIPC added to the official RV32I pass subset
- project 22
RV32I JAL official test
introduces JAL added to the official RV32I pass subset
- project 23
RV32I JALR official test
introduces JALR added to the official RV32I pass subset
- project 24
RV32I branch official tests
introduces Branch tests added to the official RV32I pass subset
- project 25
RV32I/I official test set
introduces All local official rv32i/I tests passing through the P17 harness
- project 26
RV32I ACT4 probe
introduces Reproducible ACT4 plus Sail run for the full rv32i/I test directory
- project 27
RV32I machine-mode traps and CSRs
introduces Machine-mode CSR file, trap entry, and mret return path
- project 28
RV32I machine-mode interrupts
introduces Machine timer interrupt, external IRQ, mie/mip, and mstatus interrupt stack
- project 29
RV32I MMIO platform
introduces Memory-mapped timer and UART registers on the external-memory shell
- project 30
RV32I tiny runtime
introduces Linker script, startup assembly, trap handler, and compiled UART-loaded runtime image
- project 31
RV32I C runtime probe
introduces Freestanding C main, ABI smoke, C-visible interrupt flags, and MMIO from C
- project 32
RV32IM runtime probe
introduces RV32M multiply/divide, ACT4 rv32i/M tests, and C arithmetic without avoiding hardware division
- project 33
RV32IM timing fix
introduces Iterative RV32M multiply, setup timing closure, and realistic transition repair
- project 34
RV32IM DRV cleanup
introduces Reset-tree cleanup, post-route repair, and DRV reduction
- project 35
RV32IM signoff clean
introduces Low-memory mtvec WARL cleanup, divider sign-fix simplification, and residual DRV audit
- project 36
RV32IM divider sign stage
introduces One-cycle divider sign-fix stage to clear the P35 slew/cap tail
- project 37
RV32IM Zicsr/Zifencei closure
introduces Writable mscratch and legal fence.i for the first passing CSR and instruction-fence extension batches
- project 38
Official arch-test packaging
introduces A single named DUT plugin and one make target that runs every scoped extension batch together
- project 39
RV32IM Zicntr counters
introduces cycle/time/instret CSRs - the first piece of real ISA work after the P38 packaging cleanup
- project 40
M-mode runtime API audit
introduces Full trap-frame ABI, ecall round-trip, and irq_save/irq_restore primitives - the runtime foundation FreeRTOS will inherit
- project 41
FreeRTOS port (compile-only)
introduces First third-party RTOS code in the build - FreeRTOS-Kernel V11.1.0 links against our chip with a small chip-specific port adapter
- project 42
FreeRTOS multi-task demo
introduces First real RTOS scheduling on our chip - producer/consumer/watcher tasks, timer-driven preemption, queue ops, FreeRTOS V11.1.0 unmodified
- project 43
FreeRTOS multi-task demo, hardened
introduces MMIO halt port replacing the P09-era `jal x0, 0` sentinel; first chip on the ladder hardened with a real RTOS running on it
- project 44
Framebuffer demo (chip-rendered plasma on a PC window)
introduces First demo where the chip actually generates visual output - 96x96 RGB565 plasma frames rendered by FreeRTOS, dumped from sim, played back as a pygame window
- project 45
A extension (atomics)
introduces lr.w/sc.w + 9 AMO ops on a single-hart reservation register; first Linux-path rung past the FreeRTOS milestone, hardened with 0 violations across all corners
- project 46
Zba + Zbb-essentials bitmanip
introduces 13 single-cycle bitmanip ops (Zba sh*add, Zbb logical/min/max/sext/zext) - chip ALU works, gcc-zbb auto-emit is partial
- project 47
Supervisor-mode CSR scaffolding
introduces 9 S-mode CSRs (sstatus/sie/stvec/sscratch/sepc/scause/stval/sip/satp) decoded and round-tripping as M-readable storage; staging for Linux's S-mode work
- project 48
Trap delegation CSR scaffolding
introduces medeleg/mideleg as M-readable storage; staging for the M↔S priv transition rung
- project 49
M↔S privilege mode tracking
introduces real cur_priv register, mstatus.MPP wired through trap entry/mret, ECALL cause routes by priv mode, WARL coerce on MPP
- project 50
S-mode trap routing
introduces medeleg-driven trap routing to S, sret instruction, sstatus as a real subset view of mstatus
- project 51
CSR privilege check + sie/sip subset
introduces priv-check on CSR access, mret/sret priv guard, sie/sip as subset views of mie/mip
- project 52
Sv32 page-table walker
introduces 2-level Sv32 walker for 4 KiB pages, load/store translation in S-mode, page-fault traps with VA in stval
- project 53
Walker completion (megapages + sfence.vma + AMO xlate)
introduces 4 MiB megapages, sfence.vma decoding, AMO operations through the Sv32 walker
- project 54
Platform shape (16 MiB + SBI proof of concept)
introduces external memory bumped to 16 MiB; SBI-style M-mode handler dispatching ECALL_FROM_S putchar
- project 55
Hello, S-mode kernel
introduces real C-level S-mode kernel running on identity-mapped megapages, calling SBI putchar and shutdown through M-mode firmware
- project 56
RTL completion for Linux boot
introduces hardware A/D bit updates in the Sv32 walker; CLINT-shaped timer at SiFive-standard MMIO addresses
- project 59
Linux 6.12.85 boots on a chip we built from scratch
introduces Sv32 instruction-fetch translation; the chip boots an unmodified mainline Linux kernel
- project 60
First userspace process — RV32 hello as PID 1
introduces a freestanding RV32 hello binary, an initramfs cpio embedded in the kernel, and the kernel's Run /init handoff observed end-to-end
- project 61
4-entry TLB and the chip-profiling harness
introduces a unified Sv32 TLB sitting in front of the existing P59 walker; chip-side profiling, benchmark.json emission, and the per-rung chart pack
- project 62
First userspace process prints — Zbb completion + U-mode + SUM
introduces full Zbb extension, U-mode Sv32 translation, mstatus.SUM, /dev/console in initramfs — first userspace text rendered to UART
- project 63
Single-cycle fetch on TLB hit (the easy half of a 2-stage pipeline)
introduces combinational TLB-driven mem-issue path; an annotated timeline of the full Linux boot
- project 64
Prefetch-under-writeback + Verilator dual-target sim (~270× faster iteration)
introduces prefetch path overlapped with WB; second simulator (Verilator) sharing the chip RTL with iverilog
- project 65
Fused decode/execute + skip S_MEM on register-only ops (CPI 4.29 → 3.63)
introduces untranslated-ALU 2-cycle path; P65→P64→P63 cycle-comparison stack
- project 66
D+X fused into a single execute cycle (CPI 3.63 → 2.62)
introduces combinational op_a/op_b read; S_DECODE eliminated
- project 68
AtomVM port — and the C extension we needed to get there
introduces RV32C support (decompressor, straddle-aware fetch, compressed-link addressing); AtomVM bare-metal build flow on the chip
- project 69
Framebuffer revival — pixels from the chip to a host window
introduces chip-renders-pixels / host-displays plumbing on the modern core (Verilator harness `+fb_dump`, RGB565 viewer)
- project 70
F/D FPU subset, libc revival, and AtomVM ping-pong
introduces hard-float newlib compatibility; F/D load-store and fmv bit-motion paths; small D-FPU subset for printf/dtoa; libc init in reset code; AtomVM stdlib and process ping-pong on real newlib
- project 71
AtomVM stdlib scheduler/timer stress
introduces AtomVM timer path; receive-after timeout path; multi-process stdlib workload; allocation pressure on P70 runtime
- project 72
AtomVM chip-visible I/O NIF demo
introduces AtomVM platform NIFs; Erlang-driven chip UART writes; Erlang framebuffer marker writes; frame-ready bridge from AtomVM
- project 73
AtomVM framebuffer graphics
introduces AtomVM-rendered framebuffer frames; scanline platform NIF; host GIF artifact from chip-written RGB565 memory
- project 74
AtomVM interactive game host bridge
introduces host keyboard events into Verilator; chip MMIO input queue; AtomVM Erlang game-server loop
- project 75
AtomVM Tetris
introduces 16-entry host input FIFO; Erlang process input messages; chip-side Tetris
- project 76
AtomVM batched input bridge
introduces batched host-input NIF; viewer key filtering; Tetris input bridge cleanup
- project 77
AtomVM input FIFO IRQ bridge
introduces FIFO-not-empty machine external IRQ; M-mode ack handler; AtomVM IRQ observability NIFs
- project 78
AtomVM input IRQ mailbox bridge
introduces IRQ-driven sys_poll_events FIFO drain; Erlang input mailbox messages; subscribed game process
- project 79
Linux host TTY over SBI getchar
introduces bidirectional hvc0 console input; host FIFO to SBI getchar; tiny interactive /init
- project 80
BusyBox initramfs on the capable core
introduces static RV32 musl BusyBox; Linux shell over host TTY; P78 core for Linux userspace
- project 81
BusyBox PTY console
introduces Linux devpts; BusyBox ash with a controlling terminal; raw UART screen bridge; lossless host-input handshake
- project 82
Chip-side C compiler
introduces guest-side compiler; generated RV32 Linux ELF; exec from tmpfs; TinyCC feasibility check
- project 83
TCC RV32 on chip
introduces TinyCC RV32 fork; real guest-side C compiler; static RV32 ELF output; compiler performance follow-up
- project 84
Shell profile flamegraph
introduces BusyBox shell workload benchmark; command milestone timing; PC-sample flamegraph-style profile
- project 85
BusyBox symbol profile
introduces userspace ELF symbolization; shell-window PC sample filtering; BusyBox hot-function profile
- project 86
8-entry TLB shell perf
introduces 8-entry unified TLB; shell workload before/after; BusyBox-symbolized perf regression test
- project 87
Direct UART console perf
introduces direct UART MMIO shell output; HVC/SBI console bypass measurement; P86/P87 shell workload comparison
- project 88
Memory stall attribution
introduces memory-bus request attribution; BusyBox shell stall split; open-core architecture comparison
- project 89
Tiny I-cache fetch
introduces direct-mapped instruction cache; fetch-stall reduction; first frontend step toward application-core shape
- project 90
I-cache line fill
introduces 4-word I-cache lines; blocking refill state; negative frontend result
- project 91
I-cache fill buffer
introduces critical-word-first I-cache miss handling; one-entry background fill descriptor; P90 recovery
- project 92
Fetch queue
introduces one-entry fetch queue; execute-stage next-PC prefetch; frontend decoupling measurement
- project 93
Branch predictor v0
introduces 32-entry BTB; 2-bit branch counters; 8-entry return-address stack; predictor accuracy counters
- project 94
Memory arbiter v0
introduces explicit memory request classes; arbiter want/grant counters; contention attribution behind the shared RAM port
- project 95
Store buffer v0
introduces one-entry external-RAM store buffer; store accept/drain counters; measured store-buffer negative result
- project 96
D-cache v0
introduces direct-mapped word D-cache; aligned LW hit bypass; write-through SW update; D-cache performance counters
- project 97
D-cache line-fill
introduces four-word D-cache lines; critical-word-first demand loads; background D-cache fill request class; measured line-fill negative result
- project 98
D-cache throttle
introduces frontend-aware throttling for background D-cache line fill; measured recovery from P97 shared-port regression; setup for Harvard I/D service arc
- project 99
Harvard I/D map
introduces explicit Harvard instruction/data service map; current shared-port gap list; P100 split-port acceptance criteria
- project 100
Split I/D service
introduces instruction/data service intent counters; lower shared conflict accounting; Harvard boundary evidence
- project 101
Split ITLB/DTLB
introduces separate 8-entry ITLB and DTLB banks; side-specific TLB replacement; split translation profiling
- project 102
Data-side write buffer with forwarding
introduces core-local translated store buffer; store-buffer counters; reproducible BusyBox corruption case
- project 103
Store-buffer trace and repair
introduces store-buffer transaction trace; grant-qualified store-buffer drain; BusyBox shell correctness repair
- project 104
Banked lower memory conflict counters
introduces word-interleaved lower-memory bank model; instruction/data same-bank conflict counters; split-bank opportunity accounting
- project 105
Banked lower service model
introduces read-like lower-bank service estimator; conservative side-effect classification; projected banked-memory shell speedup
- project 106
Banked lower-memory contract
introduces top-level auxiliary lower-bank read lane; Verilator-serviced banked memory contract; checksum-backed auxiliary read accounting
- project 107
Banked auxiliary D-cache fill
introduces auxiliary lower-bank response path; D-cache background-fill consumer; aux response consumption counters
- project 108
Banked auxiliary I-cache fill
introduces auxiliary instruction prefetch consumer; I-cache aux fill counter; instruction-side lower-bank response use
- project 109
Banked auxiliary demand prefetch
introduces demand-visible auxiliary prefetch bypass; S_WB store-buffer drain overlap; auxiliary demand-prefetch counter
- project 110
Tagged auxiliary response
introduces tagged auxiliary response record; owner-counted aux lane; explicit aux cancel/error fields
- project 111
Nonblocking load aux
introduces aux-owned aligned load miss; load/prefetch split-bank overlap; D-cache aux load-fill counters
- project 112
Aux response queue
introduces one-entry aux load response queue; MSHR-shaped load response record; aux queue counters
- project 113
Load miss policy
introduces aux-load issue gating; policy counters; queue-pressure measurement
- project 114
PTW aux owner
introduces PTW aux-owner counters; A/D-write block accounting; PTW negative result
- project 115
Frontend target queue
introduces FTQ metadata shadow; predicted-target record; frontend steering scaffold
- project 116
Active predictor steering
introduces guarded predictor steering; steering candidate counters; speculative-fetch failure note
- project 117
Speculative target buffer
introduces guarded one-entry speculative target buffer; userspace fault result; promote/discard counters
- project 118
LSU shape
introduces LSU-stage counters; address-generation/DTLB/S_MEM split measurement; data-side baseline
- project 119
LSU request scoreboard
introduces shadow LSU request record; in-order scoreboard busy accounting; request lifetime counters
- project 120
PRF rename sketch
introduces shadow integer PRF map; rename pressure counters; physical-tag allocation sketch
- project 121
ROB commit model
introduces one-entry shadow ROB; PRF allocation lifetime; flush/commit accounting
- project 122
Multi-entry ROB sketch
introduces four-entry shadow ROB ring; occupancy counters; free-list pressure check
- project 123
Dispatch/issue split sketch
introduces shadow dispatch queue opportunity model; frontend-ready/backend-busy counters; issue-drain pressure
- project 124
Shadow integer issue slot
introduces one-entry shadow integer issue slot; queued-instruction class counters; dependency/control/memory block accounting
- project 125
Source-ready scoreboard model
introduces shadow architectural busy-bit scoreboard; queued integer source-readiness counters; dependency split
- project 126
Memory/control holding records
introduces shadow memory holding record; shadow control holding record; class-specific backend source readiness
- project 127
Scheduler wakeup/issue eligibility
introduces shadow scheduler ready mask; class-ready pair counters; priority issue sketch
- project 128
Scheduler queue/lifetime depth
introduces per-class shadow scheduler queues; queue occupancy counters; scheduler lifetime measurement
- project 129
Scheduler arrival/service decoupling
introduces shadow frontend arrival contract; backend service counters; ready/valid boundary audit
- project 130
Ready/valid contract extraction
introduces plain RTL valid/ready/fire helper; frontend/backend contract audit; top.sv refactor scaffold
- project 131
Dispatch queue module extraction
introduces state-owning shadow dispatch queue module; ready/valid queue counters; top.sv refactor pattern
- project 132
Dispatch payload record
introduces shadow dispatch payload ownership; payload invariant counters; queue metadata capture
- project 133
Dispatch payload class audit
introduces payload class audit counters; module-owned dispatch classification proof; backend refactor decision point
- project 134
Aux load prefetch policy
introduces guarded aux-load issue; frontend-memory pivot; load-miss overlap policy
- project 135
Cache background policy audit
introduces mutually exclusive aux-load block buckets; I-cache versus D-cache background attribution; P136 policy target
- project 136
I-cache background preempt
introduces I-cache background preemption test; aggressive aux-load issue policy; measured negative shell result
- project 137
Bounded memory arbitration
introduces one-preempt I-cache arbitration bound; aux-load preemption deferral counter; tiny shell-window recovery from P136
- project 138
Debt memory arbitration
introduces I-cache repair debt counter; debt-limited aux-load preemption; debt paydown instrumentation
- project 139
I-cache repair usefulness
introduces I-cache background repair provenance tags; first-use and repeat-use fetch counters; repair usefulness ratios
- project 140
Repair-aware I-cache arbitration
introduces one-word I-cache background repair budget; repair policy stop counters; repair bandwidth tuning
- project 141
Adaptive second-word I-cache repair
introduces demand-fetch-based second-word repair budget; adaptive I-cache repair policy counter; near-P134 shell recovery
- project 142
Selective prefetch second-word I-cache repair
introduces frontend-consuming prefetch repair budget; split demand/prefetch repair grants; first post-P134 shell-window win
- project 143
Prefetch consumer repair classifier
introduces per-class I-cache repair attribution; prefetch consumer usefulness audit; P144 execute-prefetch throttle target
- project 144
Execute-prefetch repair throttle
introduces execute-prefetch second-word repair throttle; class-aware repair policy change; repair-traffic versus shell-speed tradeoff
- project 145
Conditional execute-prefetch repair
introduces conditional execute-prefetch second-word repair; negative frontend repair predicate result
- project 146
Execute-prefetch predicate audit
introduces shadow predicate attribution for execute-prefetch I-cache repair; audit-only rollback to P144 active policy
- project 147
Strict execute-prefetch guard
introduces active composite guard for execute-prefetch second-word I-cache repair; final negative result for this repair bucket