notebook · 2026 sky130A · LibreLane · OpenROAD

from zero to a tiny RISC-V

A paced walk through LibreLane, from hardening a stupid combinational counter to a hardened RV32IM + Zicsr + Zifencei + Zicntr chip that runs an unmodified FreeRTOS V11.1.0 kernel as of P43. Multi-task scheduler, queue-based message passing, timer-driven preemption, all on a sky130A GDS with zero DRC/LVS/antenna errors.

milestone reached RTOS-on-hardware: FreeRTOS scheduler runs on a hardened sky130A GDS at P43. how →

primer → / walk the ladder

recent journal

all entries →

2026-05-07 Strict execute-prefetch guard / 147_strict_execute_prefetch_guard
2026-05-07 Execute-prefetch predicate audit / 146_execute_prefetch_predicate_audit
2026-05-06 P110 tagged auxiliary response / 110_tagged_aux_response
2026-05-06 P117 - speculative target buffer guardrail / 117_speculative_target_buffer
2026-05-06 P125 - Source-ready scoreboard model / 125_source_ready_scoreboard

house rules

01 Honesty over polish. Every page either points at a real run directory + GDS path, or labels itself NOT RUN. No fake metrics.
02 One project at a time. RTL + tests + librelane config land in one shot, then a real human runs the toolchain and writes up what happened.
03 Plain Verilog where practical. SystemVerilog only when the toolchain explicitly supports it and we verify it.