Glossary · librelane-playground

ABI — Application Binary Interface: The calling-convention contract: which registers hold arguments, which are caller- vs callee-saved, how the stack frame is laid out. ilp32 and ilp32e are RV32 ABIs; the second uses fewer registers.
ALU — Arithmetic Logic Unit: The combinational circuit in a processor that does adds, subtracts, ANDs, ORs, and comparisons.
ASIC — Application-Specific Integrated Circuit: A chip whose logic is fixed at fabrication. Cheaper per-unit and lower-power than an FPGA at scale, but tape-out is irreversible.
bare-metal: Software running directly on the hardware, with no operating system underneath. Educational / embedded firmware is bare-metal; phones, laptops, servers are not.
baud: Symbols per second on a serial link. For UART, "115200 baud" means 115200 bits/second.
CDC — Clock-Domain Crossing: Any path where a signal generated by one clock is read by logic running on a different clock. Naïve crossings cause metastability; the standard fix is a two-flop synchronizer.
cell: Synonym for "standard cell" in flow context — one pre-designed gate from the PDK library.
CS — Chip Select: Active-low select line. The host pulls it low to start a transaction and high to end it.
CTS — Clock-Tree Synthesis: The flow step that builds the buffered tree distributing the clock from one input pin to every flop on the chip with minimal skew.
DEF — Design Exchange Format: A text format describing placement and routing of a design — instances, nets, and where every wire goes. The router writes DEF; downstream tools read it.
diff — diffusion: The doped silicon regions that form transistor sources and drains. Visible as wider green/teal horizontal regions under the poly stripes.
DRC — Design Rule Check: Fab-mandated geometry rules: minimum widths, spacings, enclosures. Violating one means the chip might short or open at fab.
EBREAK: A RISC-V system instruction that triggers a debug trap. Larger CPUs handle it via an exception vector; small educational cores like P09 / P12 don't implement it (gcc has flags to keep it out of generated code).
EDA — Electronic Design Automation: Umbrella term for the software that turns RTL into a manufacturable chip — synthesis, place-and-route, signoff, and the orchestration glue that runs them in order.
flop — flip-flop: A 1-bit memory cell that captures its data input on a clock edge. Every state-holding signal in a synchronous design is built from these.
FPGA — Field-Programmable Gate Array: A reconfigurable digital chip — its logic and routing are defined by a bitstream loaded at boot, so you can iterate on RTL without taping out.
FSM — Finite State Machine: A circuit whose output depends not just on its inputs but on which step of a sequence it's in. Implemented as a state register plus combinational next-state logic.
GDS — Graphic Data System (GDSII): The binary file format that fabs eat. Contains every polygon on every layer of the final chip.
GPIO — General-Purpose Input/Output: A chip pin whose direction and value are controlled by software via a register, used for misc on/off signals.
HDL — Hardware Description Language: A language for describing digital circuits — Verilog, SystemVerilog, VHDL. Often used interchangeably with "RTL".
ISA — Instruction Set Architecture: The contract between a CPU and the software that runs on it: which instructions exist, what they do, what registers and memory the program can see. RV32I is one ISA; x86-64 is another.
LEF — Library Exchange Format: A text format describing standard-cell shapes, pin locations, and routing layers. The PDK ships LEFs; the placer uses them to know where cells fit.
LFSR — Linear-Feedback Shift Register: A shift register with XOR feedback. Cheap source of pseudo-random bits — well-chosen taps cycle through every nonzero state before repeating.
LVS — Layout-vs-Schematic: A signoff check that extracts a netlist from the GDS and compares it device-by-device to the synthesized one. Catches "did the routing actually wire what we asked for".
MISO — Master In, Slave Out: The data line going from the SPI peripheral back to the host.
MMIO — Memory-Mapped I/O: A scheme where peripheral registers appear at addresses in the CPU's memory space — read/write the address, you read/write the register.
MOSI — Master Out, Slave In: The data line going from the SPI host to the peripheral.
nwell — n-type well: A doped region of substrate that hosts PMOS transistors. The biggest, lowest layer in the sky130 stack.
P&R — Place-and-Route: The flow steps that decide where each cell sits (placement) and how every signal wire gets from driver to load (routing).
PDK — Process Design Kit: The collection of files a fab provides for designing on their process — cell libraries, DRC rules, SPICE models, technology LEFs. sky130 is an open-source PDK from SkyWater.
poly — polysilicon: The conductive material used for transistor gates in sky130. Visible as thin pink vertical stripes inside cells.
PWM — Pulse-Width Modulation: Encoding an analog value as the duty cycle of a square wave. Used to dim LEDs, control motors, or generate audio.
RISC-V: An open instruction set architecture, originally a Berkeley research project. Free to implement, simple to decode, modular — a base integer ISA plus optional extensions for multiplication, floating point, atomics, etc.
ROM — Read-Only Memory: A memory whose contents are fixed at fabrication time. In small chips like P09 / P12 the "ROM" is just a SystemVerilog parameter that synth lowers into combinational logic — same gate-level effect as a real masked ROM cell.
RTL — Register-Transfer Level: The level of abstraction at which digital designers describe a chip — flip-flops and the combinational logic between them. Verilog and SystemVerilog are RTL languages.
RV32E: The "embedded" variant of 32-bit RISC-V — same instruction encoding as RV32I but only 16 registers (x0..x15). Cuts the register-file area roughly in half. gcc supports it via -march=rv32e -mabi=ilp32e.
RV32I: The 32-bit integer base of the RISC-V ISA. 32 general-purpose registers (x0..x31), no multiplier, no floating point. Project 09 implements a subset of this.
RX — Receive: The receive (listening) side of a serial link.
SCK — Serial Clock: The clock line driven by the SPI host. Both ends sample data on its edges.
shuttle: A fab run that combines many independent user projects on one die to share the tape-out cost. TT shuttles ship roughly twice a year.
SoC — System-on-Chip: A single chip that integrates a CPU, memory, and peripherals — i.e., a whole digital system on one die.
SPI — Serial Peripheral Interface: A 4-wire synchronous serial protocol (clock + select + 2 data) used to talk to flash chips, sensors, and small peripherals.
STA — Static Timing Analysis: A non-simulation method for verifying timing — the tool walks every flop-to-flop path and checks the delay against the clock period.
standard cell: A pre-designed, fixed-height layout for one logic gate (NAND, flop, mux, …) shipped by the PDK. The placer tiles them in rows; the router connects them.
TT — Tiny Tapeout: A community service that aggregates hundreds of small user designs onto a single shuttle die fabbed at SkyWater. Cost-per-project drops from "tens of thousands of dollars" to ~$300 because the mask costs are amortized across everyone on the shuttle.
TX — Transmit: The transmit (sending) side of a serial link.
UART — Universal Asynchronous Receiver/Transmitter: A two-wire serial protocol with no shared clock — both ends agree on a bit rate and the receiver samples in the middle of each bit.
via: A vertical metal connection between two routing layers (e.g., met1 to met2). Visible as small bright squares in the layout.