journal 2026-04-28

P09 — RV32I-min, the first real ISA on the ladder

p09

The first project on the ladder where the instruction encoding is the actual one published in someone else’s spec, not ours-by-convenience. RV32I-min implements the slice of RISC-V that small educational programs need.

What happened

Status: rtl-pass. Multi-cycle 5-stage FSM (same shape as P06/P07/P08, just IF/ID/EX/MEM/WB instead of FETCH/DECODE/EXECUTE/WB). 32-bit datapath. 32 × 32-bit register file with x0 hardwired. 256-byte instruction ROM (parameterized so a future Verilog $readmemh can stuff a real program into it). 256-byte data RAM.

Three test programs all PASS:

tb_demo.sv runs Fibonacci(10) and prints PC + hex IR + disassembly + key registers each FETCH cycle. Reads like a tiny gdb session.

The honesty rules from CLAUDE.md got their first real workout here. The rule is: don’t claim “this is RISC-V” without listing exact supported / unsupported instructions and saying whether compliance tests were actually run. Both the README and the project page got an explicit table:

That disclaimer matters more than the implementation does. P06’s CPU called itself a CPU because it had a control unit and a memory; P09 restrains itself from calling itself RISC-V more than the evidence allows. Ladder reaches “your code, my silicon, RISC-V conventions” without overpromising.

Receipts

Project page: /projects/09_rv32i_min/.