Long session. Four projects on the ladder now — the first two as of this morning, two more by tonight.
P03 hardening
Failed first try because of a comment-syntax mismatch in
pin_order.cfg. The LibreLane ioplace_parser only knows three token
prefixes — # for direction (#N/#E/#S/#W/#BUS_SORT), @
for annotations, $ for virtual pins. There is no comment syntax.
Lines starting with # Pin ordering for project 03. parsed as a
direction declaration with garbage after it and the flow blew up
during Odb.CustomIOPlacement. Stripped the comments, re-ran, clean.
Second run: signoff clean across the board.
- 2374 std cells (predicted 2300 — within 3%)
- +1.08 ns setup slack at 100 MHz
- 0 max-slew, 0 fanout, 0 cap, 0 antenna, 0 DRC, 0 LVS
Cleaner result than P02, which had 11 max-slew violations in slow corner. The difference is mostly that the P03 design doesn’t have any combinational chains as long as P02’s 8-LUT PWM comparator. UART tries hard not to be deep.
P04 — SPI GPIO peripheral
Two clocks meet on the same chip for the first time. Five 2-FF synchronizer chains (cs_n, sck, mosi, all 8 bits of gpio_in). MISO is the trickiest part — needs cmd_byte to be settled before loading shift_out, so the load happens on the first sck-fall after the cmd-capture sck-rise. First version of the RTL had them on the same edge and read all zeroes; pushing the load apart by a half-sck fixed it on the second sim.
Hardened in one pass after that. 3217 cells, +3.78 ns setup slack,
4 max-slew in slow corner (probably the synchronizer-output fanout to
cs_active). 0 DRC, 0 LVS.
The pin layout actually looks like a thing now: control pins on the west, SPI cluster on the north, GPIO bus on the south. Pop the chip viewer and rotate it.
Narrative review
Read all four project pages back-to-back as if I’d never seen them. Two small fixes:
- P01 and P02 each had a “what just happened?” line saying “X μm² of silicon” with the side length where the area should be (60 μm² / 100 μm²). Should be 3600 μm² / 10000 μm² (or “60 × 60 μm” / “100 × 100 μm”). Fixed.
- No forward links between project pages. Each project linked to the one before but not the one after. Added forward arrows.
- The start primer didn’t mention SystemVerilog at all, but it’s what we use from P02 onward. Added a short paragraph.
The arc is solid: P01 builds something without a clock, P02 adds the clock, P03 builds the first protocol on the clock, P04 deals with two clocks meeting. Each project introduces exactly one major concept and reuses everything that came before. The “introduces” frontmatter line on each page is doing real work.
Side quest
Killed about six stale dev-server processes that were lingering from
earlier sessions and serving stale data-store.json caches. The
“UnknownContentCollectionError” both times I added a new project
content file traces back to that — Astro’s content store is
session-cached, and adding a file from outside the dev-server’s
watcher doesn’t always invalidate it. New flow: kill the dev server
between project additions.
Status board now reads:
01 comb logic hardened
02 counter / PWM / LFSR hardened
03 UART transmitter hardened
04 SPI-ish GPIO peripheral hardened
05–10 not-started40% through the ladder.