P08 moved from RTL pass to a completed macro-aware LibreLane run.
The design is the P07 tiny SoC with its 16-byte flop RAM replaced by a
sky130_sram_1kbyte_1rw1r_8x1024_8 OpenRAM macro. The hard part was not the
bus logic; it was getting the flow to treat a fixed hard-IP GDS, LEF, Verilog
netlist, and timing library as one coherent black box.
Command:
make harden PROJECT=08_macro_integrationResult: PASS for the flow, with DRC marked PARTIAL.
| check | result |
|---|---|
| Run directory | projects/08_macro_integration/librelane/runs/RUN_2026-04-28_18-08-47 |
| Final GDS | projects/08_macro_integration/librelane/runs/RUN_2026-04-28_18-08-47/final/gds/top.gds |
| Metrics | projects/08_macro_integration/librelane/runs/RUN_2026-04-28_18-08-47/final/metrics.csv |
| Setup timing | PASS, worst setup slack 10.37 ns |
| Route DRC | PASS |
| LVS | PASS on the project page, but local metric field is UNKNOWN |
| Antenna | PASS on the project page, but local metric field is UNKNOWN |
| Macro DRC | PARTIAL because the OpenRAM macro reports known rule-deck mismatches |
The important lesson is that a macro integration run can be physically useful
without looking as tidy as a standard-cell-only run. The SRAM is fixed IP; we
do not edit its geometry. The repo records that honestly as PARTIAL rather
than pretending the macro DRC noise disappeared.
What remains: the page should keep making the DRC caveat visible, and later
macro projects should avoid rediscovering the same MACROS, power-hook, and
rendering settings from scratch.