P14 now has the persistence layer P13 was missing. The CPU is still
the same small RV32E-shaped core: 16 architectural registers, 8-word
data RAM, 32-word instruction memory. The difference is how the
instruction memory gets filled. On reset, spi_boot owns imem,
issues a JEDEC 0x03 READ to an external SPI flash, clocks in 128
bytes, writes 32 little-endian instruction words, then releases the
CPU.
RTL status: PASS. Harden status: PASS.
The strict testbench drives the chip from the TT pin side and includes
a behavioural SPI flash model preloaded with a program that prints
P14\n, halts, and leaves R5 = 14 visible on uo_out[7:3].
[ok] boot_done asserted after 4225 clocks
[uart-rx] byte 0: 0x50 ('P')
[uart-rx] byte 1: 0x31 ('1')
[uart-rx] byte 2: 0x34 ('4')
[uart-rx] byte 3: 0x0a ('?')
PASS: P14 booted from SPI flash, ran "P14\n" program, halted.The harden evidence is in
projects/14_rv32e_flash_boot/librelane/runs/RUN_2026-04-29_12-48-45:
- Final GDS:
final/gds/tt_um_librelane_p14_rv32e_flash.gds - Metrics:
final/metrics.csv - Standard cells: 15289
- Sequential cells: 2062
- Worst setup / hold slack: +0.98 ns / +0.11 ns
- Magic DRC / KLayout DRC / LVS / antenna: PASS / PASS / PASS / PASS
The run still reports max-slew, max-fanout, and max-cap warnings, similar to P13. Those are recorded in the metrics; the flow completed and produced final signoff artifacts.
The important boundary moved: P13 needed a host to reload imem after every power cycle. P14 needs only a flash chip with bytes already in it. That is the embedded-microcontroller shape: power, reset, fetch from persistent storage, run.
RISC-V honesty note: compliance tests are NOT RUN. The implemented subset is listed on the project page; this is an educational RV32E core, not a standards-complete RISC-V product.