P11 took the P06 FSM CPU wrapper through a standalone harden.
The RTL journal covered the pin-packing decision: UART TX, halted, and the
low six bits of R7 fit into uo_out; debug PC and wider internal state do not.
This follow-up records the physical result.
Command:
make harden PROJECT=11_tt_cpuResult: PASS.
| check | result |
|---|---|
| Run directory | projects/11_tt_cpu/librelane/runs/RUN_2026-04-29_11-37-33 |
| Final GDS | projects/11_tt_cpu/librelane/runs/RUN_2026-04-29_11-37-33/final/gds/tt_um_librelane_p06_cpu.gds |
| Metrics | projects/11_tt_cpu/librelane/runs/RUN_2026-04-29_11-37-33/final/metrics.csv |
| Setup timing | PASS, worst setup slack 7.32 ns |
| Route DRC | PASS |
| Magic DRC | PASS |
| KLayout DRC | PASS |
| LVS | PASS on the project page, but local metric field is UNKNOWN |
| Antenna | PASS on the project page, but local metric field is UNKNOWN |
The standalone run targets a TT 2x2-ish wrapper shape and confirms the P06 CPU can sit behind the fixed TT user-project pin frame. It still does not replace Tiny Tapeout’s official CI flow.
What remains: a real TT submission would package this wrapper in the TT template and let the shuttle flow harden it against the real mux and slot constraints.