P15 gets the 8 KiB SRAM shape

We replaced P15’s 16-byte harden placeholder with the thing we actually wanted to learn from: 8 KiB of SRAM behind the core’s byte-addressed bus. The top now uses four sky130_sram_2kbyte_1rw1r_32x512_8 macros. Each bank is 2 KiB; addr[12:11] selects the bank and addr[10:2] selects the 32-bit word inside that bank.

The top-level SRAM simulation passes the same official smoke as the core-only harness:

PASS: P15 SRAM top I-nop-00.S self-check accepted after 1067 clocks
PASS: P15 SRAM-backed top acceptance smoke complete.

The physical run took the long way around. A compact 1900 um x 1400 um floorplan got through placement but failed global routing with 10,302 overflow. Spreading the macros to the corners of a 2600 um x 1700 um die fixed routing.

Recorded run:

projects/15_rv32i_arch_test/librelane/runs/RUN_2026-04-30_10-05-37

Artifacts:

projects/15_rv32i_arch_test/librelane/runs/RUN_2026-04-30_10-05-37/final/gds/top.gds
projects/15_rv32i_arch_test/librelane/runs/RUN_2026-04-30_10-05-37/final/metrics.json

Signoff result:

check	result
Route DRC	`PASS` (`0`)
Magic DRC	`FAIL` (`22294402`)
KLayout DRC	`NOT RUN`
Macro DRC disposition	`PARTIAL` (trusted OpenRAM macro waiver)
LVS	`PASS` (`0`)
Antenna	`PASS` (`0`)
Setup timing	`PASS` (`0` violations, worst setup slack `14.085 ns`)
Hold timing	`PASS` (`0` violations, worst hold slack `0.108 ns`)
Max slew / cap checker	`PARTIAL` (`4209` slew, `156` cap warnings)

The realistic result is hardened with a trusted SRAM macro DRC waiver. The memory bus, SRAM macro placement, PDN connections, detailed routing, antenna repair, timing, and LVS all work. Raw full-chip DRC is not clean: Magic produces a giant macro-internal OpenRAM report, and KLayout DRC was skipped for this macro-waived checkpoint.

One other caveat matters: the SRAM macros are not initialized at reset. The top-level simulation preloads the behavioural macro models so we can test the adapter. Real silicon would need a loader, ROM path, scan load, or some other boot story before this is a self-contained chip.