P15 now has a completed LibreLane run. The important phrase is “bus-shell CPU”: this is the RV32I core with the byte-addressed memory bus and a 16-byte halt-loop memory placeholder, not the full 8 KiB official test RAM as standard cells.
Run:
projects/15_rv32i_arch_test/librelane/runs/RUN_2026-04-30_06-20-57Artifacts:
projects/15_rv32i_arch_test/librelane/runs/RUN_2026-04-30_06-20-57/final/gds/top.gds
projects/15_rv32i_arch_test/librelane/runs/RUN_2026-04-30_06-20-57/final/metrics.jsonSignoff result:
| check | result |
|---|---|
| Magic DRC | PASS (0) |
| KLayout DRC | PASS (0) |
| LVS | PASS (0) |
| Antenna | PASS (0) |
| Setup timing | PASS (0 violations) |
| Hold timing | PASS (0 violations) |
| Max slew / cap checker | PARTIAL (5155 slew, 59 cap warnings) |
The config change that made this useful was boring and correct: stop pretending the arch-test memory is on-chip flop RAM, keep the CPU memory bus, use a tiny placeholder for backend exploration, and relax the target from 25 ns to 40 ns. The final recorded run also uses a project-local SDC, which removes the generic fallback-SDC warnings and gives the resizer a clearer electrical target. The old wide 2400 um run already made GDS but missed setup by about 5.16 ns. The new 900 um run is much smaller and closes setup/hold.
We also removed the design-RTL timescale directive that caused hundreds
of LibreLane lint warnings and taught the local Icarus Makefile to pass
-Wno-timescale. The RTL test remains the official one-file smoke:
rv32i/I/I-nop-00.S from upstream riscv-arch-test in self-check mode.
This still does not prove RV32I compliance. It proves one official source file passes in RTL, and the physically explored core-plus-bus shell can complete LibreLane. A real memory target is still an SRAM integration problem.