P17 turns memory skips into real arch-test failures

P16 answered one question and exposed another. The UART loader worked, but the 8 KiB SRAM meant most official rv32i/I self-check images were too large to run.

P17 keeps the core and loader, then exports the memory bus. The testbench connects that bus to a 256 KiB behavioral memory model. This is not pretending we hardened 256 KiB of SRAM; it is a way to make the official tests execute.

Command:

make -C projects/17_rv32i_external_mem/test batch

Result:

Passing:

Everything else reaches RVMODEL_HALT_FAIL, visible as x5 = 31. That is not great, but it is much better than the P16 answer. We now know the next work is architectural debug, not loader plumbing or memory capacity.

No LibreLane run yet. The config is a logic-only target with external memory pins; a physical version would need a real memory system on the other side of that bus.