P17 now has a real LibreLane run. The design still uses a behavioral 256 KiB memory model for the official-test batch, but the chip that got hardened is the logic-only CPU/loader shell with an exposed external memory bus.
Command:
make harden PROJECT=17_rv32i_external_memResult: PASS
| field | value |
|---|---|
| Run directory | projects/17_rv32i_external_mem/librelane/runs/RUN_2026-04-30_17-22-47 |
| Final GDS | projects/17_rv32i_external_mem/librelane/runs/RUN_2026-04-30_17-22-47/final/gds/top.gds |
| Metrics | projects/17_rv32i_external_mem/librelane/runs/RUN_2026-04-30_17-22-47/final/metrics.json |
| Route DRC | PASS (0) |
| Magic DRC | PASS (0) |
| KLayout DRC | PASS (0) |
| LVS | PASS (0) |
| Antenna | PASS (0) |
| Setup timing | PASS (0 violations, worst setup slack 10.306 ns) |
| Hold timing | PASS (0 violations, worst hold slack 0.105 ns) |
Before rerunning the flow, the P17 SDC got the same basic treatment as P16:
exclude clk from the generic input-delay group, add IO drive/load context,
and keep the clock handling explicit. That removed the avoidable clock
input-delay warning.
The manufacturability checks are clean. The remaining backend warnings are not fake-zeroed:
| warning | result |
|---|---|
| Max slew checker | PARTIAL (2971 warnings) |
| Max capacitance checker | PARTIAL (29 warnings) |
| Floating-net checker | PARTIAL (2 warnings) |
| IR-drop setup | PARTIAL (VSRC_LOC_FILES not provided) |
This does not change the architecture result. P17 still has 2 PASS, 37
FAIL, and 0 NOT RUN across the official rv32i/I batch. The value of
this run is narrower but useful: the external-memory version is physically
buildable as a logic shell, so the next round can focus on architectural
debug instead of debating whether the project can reach GDS.