P27 adds the first machine-mode trap path

After the ACT4 rv32i/I pass, the next useful RISC-V step was not another integer instruction. It was the first machine-mode substrate.

P27 adds:

CSR read/write instructions;
mstatus, misa, mtvec, mepc, mcause, and mtval;
ecall;
ebreak;
illegal-instruction trap entry;
misaligned load/store trap entry;
mret.

Command:

make -C projects/27_rv32i_machine_traps/test

Result: PASS

The directed testbench runs six small hand-encoded programs:

test	result
CSR read/write and immediate set	`PASS`
`ecall` trap and `mret` resume	`PASS`
illegal-instruction trap and `mret` resume	`PASS`
`ebreak` trap and `mret` resume	`PASS`
misaligned load trap	`PASS`
misaligned store trap	`PASS`

Later in the same session, P27 got its own LibreLane config, reran the ACT4/Sail base-integer directory on the modified core, and hardened. The follow-up result is recorded in the P27 hardening journal entry.

This is still not full compliance. It is the first point where the core can run a software trap handler instead of treating unsupported behavior as a terminal simulator halt.

Next best step: timer and external interrupts. The trap path exists now; it needs an event source.