journal 2026-05-01

P28 adds timer and external interrupts

p28riscvinterruptsact4

P28 takes the P27 trap path and gives it event sources.

Commands:

make -C projects/28_rv32i_machine_interrupts/test
make -C projects/28_rv32i_machine_interrupts/test act4

Results:

checkresult
Directed CSR/trap regressionPASS
Masked timer pending testPASS
Timer interrupt with mretPASS
External interrupt handlerPASS
ACT4/Sail rv32i/IPASS=39 FAIL=0 NOT RUN=0
HardeningNOT RUN
Official privileged testsNOT RUN

The useful part is that the interrupt plumbing did not disturb the base integer ACT4 result. The honest caveat is that the timer registers are custom teaching CSRs at 0x7c0 and 0x7c1; real RISC-V platforms normally expose mtime and mtimecmp as memory-mapped platform registers.

Next, P29 should stop using that shortcut and make a real small-system memory map: ROM, RAM, UART, timer MMIO, and external interrupt wiring.