P36 clears the divider slew/cap tail

P36 followed the P35 result directly. P35 was DRC/LVS/antenna clean and passed the ACT4 I/M batches, but the routed metrics still had 13 max-slew and 1 max-cap violations. The remaining suspect was the signed divide/remainder finish path.

The RTL change is intentionally small:

add S_DIV_SIGN
register the raw final quotient-or-remainder
register the final sign-correction bit
apply the two’s-complement sign fix one cycle later

Commands:

make -C projects/36_rv32im_divider_sign_stage/test clean all
make -C projects/36_rv32im_divider_sign_stage/test act4_m
make -C projects/36_rv32im_divider_sign_stage/test act4
make harden PROJECT=36_rv32im_divider_sign_stage

Result:

check	result
Directed RV32IM runtime	`PASS`
ACT4/Sail `rv32i/I`	`PASS=39 FAIL=0 NOT RUN=0`
ACT4/Sail `rv32i/M`	`PASS=8 FAIL=0 NOT RUN=0`
Full RISC-V compliance	`NOT RUN`
LibreLane flow	`PASS`
Run directory	`projects/36_rv32im_divider_sign_stage/librelane/runs/RUN_2026-05-01_20-53-59`
Final GDS	`projects/36_rv32im_divider_sign_stage/librelane/runs/RUN_2026-05-01_20-53-59/final/gds/top.gds`
Metrics	`projects/36_rv32im_divider_sign_stage/librelane/runs/RUN_2026-05-01_20-53-59/final/metrics.json`
Magic DRC	`PASS` (`0` errors)
KLayout DRC	`PASS` (`0` errors)
LVS	`PASS` (`0` errors)
Antenna	`PASS` (`0` net violations, `0` pin violations)
Routing DRC	`PASS` (`0` errors)
Setup timing	`PASS` (`0` violations, worst setup slack `6.626 ns`)
Hold timing	`PASS` (`0` violations, worst hold slack `0.106 ns`)
Max slew	`PASS` (`0` violations)
Max cap	`PASS` (`0` violations)
Max fanout	`FAIL` (`1` violation)

Compared with P35, standard-cell count moved from 26883 to 27181, and standard-cell area moved from 188652 um^2 to 191266 um^2. Setup slack fell from 8.048 ns to 6.626 ns, but that is still comfortable against the 40 ns clock.

The honest read: this fixed the thing we were aiming at. It did not produce a perfect DRV-zero metrics file because of the one fanout count. That is a much smaller problem than the P35 slew/cap tail.