After the clean P36 harden, the useful question was no longer “can this RV32IM core pass the I and M batches?” It can. The useful question became “what is the first official-test wall after that?”
So P36 now has a compliance addendum instead of spawning a new project just for packaging:
| suite | result |
|---|---|
ACT4/Sail rv32i/I | PASS=39 FAIL=0 NOT RUN=0 |
ACT4/Sail rv32i/M | PASS=8 FAIL=0 NOT RUN=0 |
ACT4/Sail rv32i/Zicsr | PASS=0 FAIL=6 NOT RUN=0 |
ACT4/Sail rv32i/Zifencei | PASS=0 FAIL=1 NOT RUN=0 |
| Full RISC-V compliance | PARTIAL |
The new result file is
projects/36_rv32im_divider_sign_stage/compliance/SWEEP.md.
The failure shape is useful. All six CSR instruction forms fail in the ACT4
self-check harness, which means the next real architecture project should close
full Zicsr behavior instead of adding unrelated ISA features. fence.i also
fails as its own extension-level test, so it should be handled explicitly after
the CSR work.
Everything else remains honest NOT RUN: atomics, compressed, bitmanip,
floating point, cache-block operations, counters, crypto, supervisor mode, PMP,
virtual memory, delegation, and full privileged compliance.