P36 already did the architectural job: move the signed divide/remainder final
correction into S_DIV_SIGN, keep the ACT4/Sail I/M batches green, and clear
the P35 slew/cap tail. The remaining annoyance was purely backend-shaped:
RUN_2026-05-01_20-53-59 still had one max-fanout violation, a 14-load
branch against the same fanout-13 signoff target P35 used.
The cleanup was to make place-and-route work a little harder than signoff. The
main p36.sdc still defines the clock, IO delays, output loads, and electrical
limits, but MAX_FANOUT_CONSTRAINT is now 12 during PnR. Post-PnR STA reads
p36_signoff.sdc, which keeps the accepted signoff fanout limit at 13.
That produced a clean harden:
| check | result |
|---|---|
| LibreLane flow | PASS |
ACT4/Sail rv32i/I | PASS=39 FAIL=0 NOT RUN=0 |
ACT4/Sail rv32i/M | PASS=8 FAIL=0 NOT RUN=0 |
| Full RISC-V compliance | NOT RUN |
| Run directory | projects/36_rv32im_divider_sign_stage/librelane/runs/RUN_2026-05-02_21-18-57 |
| Final GDS | projects/36_rv32im_divider_sign_stage/librelane/runs/RUN_2026-05-02_21-18-57/final/gds/top.gds |
| Metrics | projects/36_rv32im_divider_sign_stage/librelane/runs/RUN_2026-05-02_21-18-57/final/metrics.json |
| Magic DRC | PASS (0 errors) |
| KLayout DRC | PASS (0 errors) |
| LVS | PASS (0 errors) |
| Antenna | PASS (0 net violations, 0 pin violations) |
| Route DRC | PASS (0 errors) |
| Setup timing | PASS (0 violations, worst setup slack 5.903 ns) |
| Hold timing | PASS (0 violations, worst hold slack 0.070 ns) |
| Max slew | PASS (0 violations) |
| Max cap | PASS (0 violations) |
| Max fanout | PASS (0 violations against signoff limit 13) |
The standard-cell count is 27223, with 191659 um^2 of standard-cell area.
That is a little larger and slower than P35, but this is the clean RV32IM
endpoint we wanted before moving to the next rung.