Tiny FSM CPU

`default_nettype none

module top (
    input  logic        clk,
    input  logic        rst_n,
    input  logic        start,        // currently unused (1 = run)
    // UART pacing: clocks-per-bit minus 1. At 100 MHz, 868 → 115200 baud.
    // Driven externally so the testbench can speed it up for sim.
    input  logic [15:0] baud_div,
    output logic [7:0]  out,
    output logic [4:0]  pc_out,
    output logic        halted,
    // UART tx pin (idle-high). Pulled out of the chip; off-chip a
    // standard 3.3V serial monitor at the matching baud rate decodes
    // the bytes the OUT instruction sent.
    output logic        uart_tx
);

  localparam int ROM_DEPTH = 32;

  // Encoder helpers — used only inside the localparam ROM init below,
  // so they must be valid in Yosys's SV frontend. We use the Verilog
  // function-name-assignment form (no `return` statement) and avoid
  // `automatic`, since Yosys's read_verilog rejects `return {...}`
  // inside automatic functions.
  function [15:0] op_alu(input [3:0] opcode,
                          input [2:0] rd,
                          input [2:0] ra,
                          input [2:0] rb);
    op_alu = {opcode, rd, ra, rb, 3'b000};
  endfunction
  function [15:0] op_unary(input [3:0] opcode,
                            input [2:0] rd,
                            input [2:0] ra);
    op_unary = {opcode, rd, ra, 3'b000, 3'b000};
  endfunction
  function [15:0] op_ldi(input [2:0] rd,
                          input [7:0] imm);
    op_ldi = {4'hA, rd, imm, 1'b0};
  endfunction
  function [15:0] op_jmp(input [3:0] opcode,
                          input [4:0] addr);
    op_jmp = {opcode, 7'b0000000, addr};       // 4 + 7 + 5 = 16 bits
  endfunction

  // ROM is held as a packed bit-vector — 32 instructions × 16 bits =
  // 512 bits. Iverilog doesn't accept unpacked array parameters, but
  // is fine with packed bit-vectors. We slice the current word with a
  // `+:` index. Concatenation order is MSB-first, so PC=31 sits at
  // the top and PC=0 at the bottom.
  localparam int PROG_BITS = ROM_DEPTH * 16;

  // Default boot program: Fibonacci(6) into R1..R6, then HLT. R7 ends
  // up holding the last value (matches the `out` port). Testbench
  // overrides this via parameter when it wants to exercise different
  // instructions. Listed PC=31 first → PC=0 last.
  localparam logic [PROG_BITS-1:0] DEFAULT_PROG = {
    {24{16'h0000}},                                // 31..08: zero-fill
    op_jmp (4'hF, 5'd0),                           // 07: HLT (jump field unused)
    op_unary(4'h8, 3'd7, 3'd6),                    // 06: R7 = R6 (= out)
    op_alu (4'h0, 3'd6, 3'd4, 3'd5),               // 05: R6 = R4 + R5 = 8
    op_alu (4'h0, 3'd5, 3'd3, 3'd4),               // 04: R5 = R3 + R4 = 5
    op_alu (4'h0, 3'd4, 3'd2, 3'd3),               // 03: R4 = R2 + R3 = 3
    op_alu (4'h0, 3'd3, 3'd1, 3'd2),               // 02: R3 = R1 + R2 = 2
    op_ldi (3'd2, 8'h01),                          // 01: R2 = 1
    op_ldi (3'd1, 8'h01)                           // 00: R1 = 1
  };

  parameter logic [PROG_BITS-1:0] PROG = DEFAULT_PROG;

  logic [4:0]  pc;
  logic [15:0] ir;

  wire [3:0] dec_op  = ir[15:12];
  wire [2:0] dec_rd  = ir[11: 9];
  wire [2:0] dec_ra  = ir[ 8: 6];
  wire [2:0] dec_rb  = ir[ 5: 3];
  wire [7:0] dec_imm = ir[ 8: 1];      // LDI imm payload (bit 0 reserved)
  wire [4:0] dec_addr= ir[ 4: 0];      // branch/jump target

  // Map CPU opcode to ALU op (a 4-bit code matching the P05 ALU).
  // Most ALU opcodes are 1:1 with their CPU encoding. CMP routes
  // through SUB (subtractor compute, no register write).
  logic [3:0] alu_op;
  always_comb begin
    unique case (dec_op)
      4'h0: alu_op = 4'b0000;            // ADD
      4'h1: alu_op = 4'b0001;            // SUB
      4'h2: alu_op = 4'b0010;            // AND
      4'h3: alu_op = 4'b0011;            // OR
      4'h4: alu_op = 4'b0100;            // XOR
      4'h5: alu_op = 4'b0101;            // SHL
      4'h6: alu_op = 4'b0110;            // SHR
      4'h7: alu_op = 4'b1000;            // OUT — passthrough A; UART side-effect handled below
      4'h8: alu_op = 4'b1000;            // MOV
      4'h9: alu_op = 4'b1001;            // NOT
      4'hA: alu_op = 4'b1000;            // LDI uses MOV-with-imm (handled by use_imm)
      4'hB: alu_op = 4'b0001;            // CMP routes through SUB
      default: alu_op = 4'b1000;         // JMP/BZ/BNZ/HLT — datapath idle
    endcase
  end

  // Per-instruction control signals (combinational from dec_op).
  wire is_out     = (dec_op == 4'h7);              // UART send (replaces SAR)
  wire is_alu_rr  = (dec_op <= 4'h9) && !is_out;   // ALU writeback ops
  wire is_ldi     = (dec_op == 4'hA);
  wire is_cmp     = (dec_op == 4'hB);
  wire is_jmp     = (dec_op == 4'hC);
  wire is_bz      = (dec_op == 4'hD);
  wire is_bnz     = (dec_op == 4'hE);
  wire is_hlt     = (dec_op == 4'hF);
  wire is_branch  = is_jmp | is_bz | is_bnz;
  // Some ops don't update flags (MOV, OUT, LDI, branches/halt, CMP only
  // updates flags — but its result isn't written back).
  wire flag_update = ~(dec_op == 4'h8 || is_out || is_ldi || is_branch || is_hlt);
  // Register-write enable: any ALU op (excluding CMP and OUT) writes rd.
  // LDI also writes. R0 is hardwired to zero in the regfile so writes
  // there are dropped.
  wire reg_write   = (is_alu_rr || is_ldi) && (dec_rd != 3'd0);

  logic [7:0] regs [0:7];
  logic [3:0] flags_q;        // {Z, N, C, V}

  // Decode-stage operand registers (so the ALU compute is a separate
  // pipeline-ish stage from regfile read).
  logic [7:0] op_a;
  logic [7:0] op_b;
  // Execute-stage result register, fed to writeback.
  logic [7:0] result_q;
  logic [3:0] flags_d;        // computed in EXECUTE, captured at WB

  // Async regfile read selectors. (R0 reads as 0, writes ignored.)
  // Verilog-2001 style — Yosys's read_verilog rejects `return` inside
  // an automatic function.
  function [7:0] reg_read(input [2:0] sel);
    if (sel == 3'd0) reg_read = 8'h00;
    else             reg_read = regs[sel];
  endfunction

  // ---- ALU: same shape as P05 ----
  wire [7:0] a_data = op_a;
  wire [7:0] b_data = op_b;
  wire [8:0] add_w  = {1'b0, a_data} + {1'b0, b_data};
  wire [8:0] sub_w  = {1'b0, a_data} - {1'b0, b_data};

  logic [7:0] alu_y;
  logic       c_out, v_out;
  always_comb begin
    alu_y = 8'h00;
    c_out = 1'b0;
    v_out = 1'b0;
    unique case (alu_op)
      4'b0000: begin alu_y = add_w[7:0]; c_out = add_w[8];
                     v_out = (a_data[7] == b_data[7]) && (alu_y[7] != a_data[7]); end
      4'b0001: begin alu_y = sub_w[7:0]; c_out = sub_w[8];
                     v_out = (a_data[7] != b_data[7]) && (alu_y[7] != a_data[7]); end
      4'b0010: alu_y = a_data & b_data;
      4'b0011: alu_y = a_data | b_data;
      4'b0100: alu_y = a_data ^ b_data;
      4'b0101: begin alu_y = {a_data[6:0], 1'b0}; c_out = a_data[7]; end
      4'b0110: begin alu_y = {1'b0, a_data[7:1]}; c_out = a_data[0]; end
      4'b0111: begin alu_y = {a_data[7], a_data[7:1]}; c_out = a_data[0]; end
      4'b1000: alu_y = a_data;
      4'b1001: alu_y = ~a_data;
      default: alu_y = a_data;
    endcase
  end
  wire z_out = (alu_y == 8'h00);
  wire n_out =  alu_y[7];

  typedef enum logic [2:0] {
    S_FETCH   = 3'd0,
    S_DECODE  = 3'd1,
    S_EXECUTE = 3'd2,
    S_WB      = 3'd3,
    S_HALT    = 3'd4
  } state_t;

  state_t state, next_state;

  // UART transmitter signals (the submodule is instantiated below).
  // We pulse uart_start_pulse for one cycle as the FSM moves from
  // EXECUTE to WB on an OUT instruction. The UART then asserts
  // uart_busy until the byte (start + 8 data + stop) finishes
  // transmitting; the FSM stalls in S_WB while busy is high.
  logic       uart_start_pulse;
  logic [7:0] uart_data;
  logic       uart_busy;

  always_comb begin
    next_state = state;
    unique case (state)
      S_FETCH:   next_state = S_DECODE;
      S_DECODE:  next_state = S_EXECUTE;
      S_EXECUTE: next_state = S_WB;
      S_WB: begin
        // OUT stalls in WB until the UART finishes transmitting. Once
        // uart_busy drops we proceed to the next instruction.
        if (is_out && uart_busy)      next_state = S_WB;
        else if (is_hlt)              next_state = S_HALT;
        else                          next_state = S_FETCH;
      end
      S_HALT:    next_state = S_HALT;
      default:   next_state = S_FETCH;
    endcase
  end

  // UART transmitter signals (the submodule is instantiated below).
  // We pulse uart_start_pulse for one cycle as the FSM moves from
  // EXECUTE to WB on an OUT instruction. The UART then asserts
  // uart_busy until the byte (start + 8 data + stop) finishes
  // transmitting; the FSM stalls in S_WB while busy is high.
  logic       uart_start_pulse;
  logic [7:0] uart_data;
  logic       uart_busy;

  always_comb begin
    next_state = state;
    unique case (state)
      S_FETCH:   next_state = S_DECODE;
      S_DECODE:  next_state = S_EXECUTE;
      S_EXECUTE: next_state = S_WB;
      S_WB: begin
        // OUT stalls in WB until the UART finishes transmitting. Once
        // uart_busy drops we proceed to the next instruction.
        if (is_out && uart_busy)      next_state = S_WB;
        else if (is_hlt)              next_state = S_HALT;
        else                          next_state = S_FETCH;
      end
      S_HALT:    next_state = S_HALT;
      default:   next_state = S_FETCH;
    endcase
  end

  // Pulse uart_start for exactly one cycle: when we're moving out of
  // EXECUTE on an OUT and have just latched op_a as the byte to send.
  assign uart_start_pulse = (state == S_EXECUTE) && is_out;
  // The byte to send is sitting in op_a (we routed regs[ra] there in
  // DECODE; the ALU's MOV passthrough also computed result_q = op_a in
  // EXECUTE, but op_a is one cycle earlier so latency is identical).
  assign uart_data        = op_a;

  // Branch resolution — happens in WB stage.
  // (Computed combinationally from flags_q, since flags from the *just-
  // executed* instruction haven't been latched yet — they're in flags_d
  // mid-EXECUTE/WB. For simplicity, branches consume flags from the
  // most recently captured flag register, so a CMP must complete one
  // full instruction before the BZ/BNZ that depends on it.)
  wire take_branch = is_jmp
                   || (is_bz  &&  flags_q[3])
                   || (is_bnz && ~flags_q[3]);

  integer i;
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state    <= S_FETCH;
      pc       <= 5'd0;
      ir       <= 16'h0000;
      op_a     <= 8'h00;
      op_b     <= 8'h00;
      result_q <= 8'h00;
      flags_d  <= 4'h0;
      flags_q  <= 4'h0;
      for (i = 0; i < 8; i = i + 1) regs[i] <= 8'h00;
    end else begin
      state <= next_state;
      unique case (state)
        S_FETCH: begin
          ir <= PROG[16*pc +: 16];
          // PC advances on FETCH; branches override in WB.
          pc <= pc + 5'd1;
        end
        S_DECODE: begin
          // LDI: route imm through op_a so the ALU's MOV (a-passthrough)
          // writes it back to rd. ra/rb are unused for LDI.
          op_a <= is_ldi ? dec_imm : reg_read(dec_ra);
          op_b <= reg_read(dec_rb);
        end
        S_EXECUTE: begin
          result_q <= alu_y;
          flags_d  <= {z_out, n_out, c_out, v_out};
        end
        S_WB: begin
          if (reg_write) regs[dec_rd] <= result_q;
          if (flag_update || is_cmp) flags_q <= flags_d;
          if (is_branch && take_branch) pc <= dec_addr;
        end
        S_HALT: ;
        default: ;
      endcase
    end
  end

  // ---- outputs ----
  assign out    = regs[7];
  assign pc_out = pc;
  assign halted = (state == S_HALT);

  // start input reserved for future use (single-step / run gate).
  // Tie off the lint warning explicitly.
  wire _unused = &{1'b0, start};

endmodule

// ---------------------------------------------------------------------
// uart_tx — 8N1 UART transmitter, lifted from project 03.
//
// Pulse `start` for one cycle with `data` valid; tx will then drive the
// start bit, 8 data bits LSB-first, and a stop bit, with each bit held
// for `baud_div + 1` clock cycles. busy stays high for the duration so
// the host can poll-and-wait. Idle line level is high.
// ---------------------------------------------------------------------
module uart_tx (
    input  logic         clk,
    input  logic         rst_n,
    input  logic         start,
    input  logic [7:0]   data,
    input  logic [15:0]  baud_div,
    output logic         tx,
    output logic         busy
);

  typedef enum logic [3:0] {
    U_IDLE  = 4'd0,
    U_START = 4'd1,
    U_D0    = 4'd2,  U_D1 = 4'd3,  U_D2 = 4'd4,  U_D3 = 4'd5,
    U_D4    = 4'd6,  U_D5 = 4'd7,  U_D6 = 4'd8,  U_D7 = 4'd9,
    U_STOP  = 4'd10
  } ustate_t;

  ustate_t ustate, ustate_next;

  logic [15:0] baud_cnt;
  logic        bit_tick;
  assign bit_tick = (baud_cnt == 16'd0);

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)                     baud_cnt <= 16'd0;
    else if (ustate == U_IDLE)      baud_cnt <= baud_div;
    else if (bit_tick)              baud_cnt <= baud_div;
    else                            baud_cnt <= baud_cnt - 16'd1;
  end

  // Latch data on entry to U_START.
  logic [7:0] data_q;
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n)                              data_q <= 8'h00;
    else if (ustate == U_IDLE && start)      data_q <= data;
  end

  always_comb begin
    ustate_next = ustate;
    unique case (ustate)
      U_IDLE:  if (start)    ustate_next = U_START;
      U_START: if (bit_tick) ustate_next = U_D0;
      U_D0:    if (bit_tick) ustate_next = U_D1;
      U_D1:    if (bit_tick) ustate_next = U_D2;
      U_D2:    if (bit_tick) ustate_next = U_D3;
      U_D3:    if (bit_tick) ustate_next = U_D4;
      U_D4:    if (bit_tick) ustate_next = U_D5;
      U_D5:    if (bit_tick) ustate_next = U_D6;
      U_D6:    if (bit_tick) ustate_next = U_D7;
      U_D7:    if (bit_tick) ustate_next = U_STOP;
      U_STOP:  if (bit_tick) ustate_next = U_IDLE;
      default:               ustate_next = U_IDLE;
    endcase
  end

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) ustate <= U_IDLE;
    else        ustate <= ustate_next;
  end

  always_comb begin
    unique case (ustate)
      U_IDLE:  tx = 1'b1;
      U_START: tx = 1'b0;
      U_D0:    tx = data_q[0];
      U_D1:    tx = data_q[1];
      U_D2:    tx = data_q[2];
      U_D3:    tx = data_q[3];
      U_D4:    tx = data_q[4];
      U_D5:    tx = data_q[5];
      U_D6:    tx = data_q[6];
      U_D7:    tx = data_q[7];
      U_STOP:  tx = 1'b1;
      default: tx = 1'b1;
    endcase
  end

  assign busy = (ustate != U_IDLE);

endmodule

// Project 06 testbench — verifying TB for the tiny FSM CPU.
//
// Strategy: run the DUT's default boot program (Fibonacci(6) into
// R1..R6, then HLT into R7). Wait for `halted` to assert, then
// peek at R1..R7 by reading the testbench's view of the regfile via
// hierarchical access.
//
// We also exercise:
//   - LDI to a few different registers and values.
//   - ADD/SUB/AND/OR/XOR with reg-reg operands.
//   - CMP + BZ/BNZ branch flow.
//   - JMP forward / loop.
//   - HLT terminates the FSM in the S_HALT state.
//
// Each test reuses the DUT but with a different program loaded via the
// PROG parameter. `top` accepts PROG as a localparam-overridable
// parameter; we instantiate one DUT per test program (each with its
// own `top` instance scoped to a separate `generate` block).

`timescale 1ns/1ps
`default_nettype none

module tb;

  // 100 MHz chip clock.
  logic clk = 0;
  always #5 clk = ~clk;

  logic rst_n;
  logic start = 1'b1;

  int errors = 0;
  int test_num = 0;

  // ---- helpers ---------------------------------------------------------

  // Apply reset and release on the next negedge.
  task automatic do_reset;
    begin
      rst_n = 1'b0;
      repeat (4) @(posedge clk);
      @(negedge clk); rst_n = 1'b1;
    end
  endtask

  // ---- instruction encoders, kept in sync with top.sv ------------------
  // Replicated here because functions inside the DUT aren't visible
  // through hierarchical reference for parameter computation.
  function automatic logic [15:0] enc_alu(input logic [3:0] op,
                                            input logic [2:0] rd,
                                            input logic [2:0] ra,
                                            input logic [2:0] rb);
    return {op, rd, ra, rb, 3'b000};
  endfunction
  function automatic logic [15:0] enc_unary(input logic [3:0] op,
                                              input logic [2:0] rd,
                                              input logic [2:0] ra);
    return {op, rd, ra, 3'b000, 3'b000};
  endfunction
  function automatic logic [15:0] enc_ldi(input logic [2:0] rd,
                                            input logic [7:0] imm);
    return {4'hA, rd, imm, 1'b0};
  endfunction
  function automatic logic [15:0] enc_jmp(input logic [3:0] op,
                                            input logic [4:0] addr);
    return {op, 7'b0000000, addr};
  endfunction
  function automatic logic [15:0] enc_hlt;
    return {4'hF, 12'h000};
  endfunction

  // ---- Test 1: default Fibonacci program (uses DUT's built-in PROG) ---

  // Baud divider — shared across all DUTs. Set to a small value so
  // OUT-driven UART transmissions complete quickly in sim. (Real
  // hardware uses something like 868 for 115200 @ 100 MHz; sim doesn't
  // care about the wire-level timing as long as it's not zero.)
  logic [15:0] baud_div = 16'd3;

  logic [7:0] dut1_out;
  logic [4:0] dut1_pc;
  logic       dut1_halted;
  logic       dut1_tx;
  top dut1 (.clk(clk), .rst_n(rst_n), .start(start), .baud_div(baud_div),
            .out(dut1_out), .pc_out(dut1_pc), .halted(dut1_halted),
            .uart_tx(dut1_tx));

  // ---- Test 2: branching / loop program ------------------------------
  // Counts down from 5 in R1 to 0 using SUB + BNZ.
  // Final R1 = 0, R7 (loop counter via copy) = number of iterations = 5.
  //
  //   00 LDI R1, 5
  //   01 LDI R2, 0           ; iteration counter
  //   02 SUB R1, R1, R3       ; R3 = 0 (R0 = 0; using R3=0 since not loaded)
  //                            actually use a constant: SUB R1,R1,R0 won't
  //                            work because R0 = 0 → R1 = R1 - 0; we want
  //                            decrement by 1. Use ADD R1, R1, R7 where R7
  //                            is loaded with -1 (0xFF) first.
  //   ... rewritten:
  //
  //   00 LDI R7, 0xFF        ; R7 = -1
  //   01 LDI R1, 5           ; R1 = 5 (loop count)
  //   02 LDI R2, 0           ; R2 = 0 (iteration tally)
  //   03 LDI R3, 1           ; R3 = 1 (increment for tally)
  // loop:
  //   04 ADD R1, R1, R7      ; R1 = R1 - 1 (since R7 = 0xFF wraps as -1)
  //   05 ADD R2, R2, R3      ; R2 += 1
  //   06 CMP R1, R0          ; compare R1 with 0; sets Z if R1 == 0
  //   07 BNZ 04              ; loop if R1 != 0
  //   08 MOV R7, R2          ; final tally → R7 (= out)
  //   09 HLT
  // Packed bit-vector programs — concatenation order is MSB-first, so
  // PC=31 sits at the top of the {} list and PC=0 at the bottom.
  localparam int PROG_BITS = 32 * 16;
  localparam logic [PROG_BITS-1:0] PROG_LOOP = {
    {22{16'h0000}},                                // 31..10
    enc_hlt(),                                      // 09 HLT
    enc_unary(4'h8, 3'd7, 3'd2),                    // 08 MOV R7,R2
    enc_jmp (4'hE, 5'd4),                           // 07 BNZ 04
    enc_alu (4'hB, 3'd0, 3'd1, 3'd0),               // 06 CMP R1,R0
    enc_alu (4'h0, 3'd2, 3'd2, 3'd3),               // 05 ADD R2,R2,R3
    enc_alu (4'h0, 3'd1, 3'd1, 3'd7),               // 04 ADD R1,R1,R7
    enc_ldi (3'd3, 8'd1),                           // 03 R3 = 1
    enc_ldi (3'd2, 8'd0),                           // 02 R2 = 0
    enc_ldi (3'd1, 8'd5),                           // 01 R1 = 5
    enc_ldi (3'd7, 8'hFF)                           // 00 R7 = -1
  };

  logic [7:0] dut2_out;
  logic [4:0] dut2_pc;
  logic       dut2_halted;
  logic       dut2_tx;
  top #(.PROG(PROG_LOOP)) dut2 (.clk(clk), .rst_n(rst_n), .start(start), .baud_div(baud_div),
                                  .out(dut2_out), .pc_out(dut2_pc), .halted(dut2_halted),
                                  .uart_tx(dut2_tx));

  // ---- Test 3: bitwise + JMP-forward (skip-over) -----------------------
  //   00 LDI R1, 0xF0
  //   01 LDI R2, 0x0F
  //   02 OR  R3, R1, R2      ; R3 = 0xFF
  //   03 JMP 06              ; skip the AND
  //   04 AND R3, R1, R2      ; would set R3 = 0 if reached
  //   05 HLT
  //   06 MOV R7, R3          ; R7 = 0xFF (proves we jumped past the AND)
  //   07 HLT
  localparam logic [PROG_BITS-1:0] PROG_JMP = {
    {24{16'h0000}},                                // 31..08
    enc_hlt(),                                      // 07 HLT
    enc_unary(4'h8, 3'd7, 3'd3),                    // 06 MOV R7,R3
    enc_hlt(),                                      // 05 HLT
    enc_alu (4'h2, 3'd3, 3'd1, 3'd2),               // 04 AND R3,R1,R2 (skipped)
    enc_jmp (4'hC, 5'd6),                           // 03 JMP 06
    enc_alu (4'h3, 3'd3, 3'd1, 3'd2),               // 02 OR R3,R1,R2
    enc_ldi (3'd2, 8'h0F),                          // 01 R2 = 0x0F
    enc_ldi (3'd1, 8'hF0)                           // 00 R1 = 0xF0
  };

  logic [7:0] dut3_out;
  logic [4:0] dut3_pc;
  logic       dut3_halted;
  logic       dut3_tx;
  top #(.PROG(PROG_JMP)) dut3 (.clk(clk), .rst_n(rst_n), .start(start), .baud_div(baud_div),
                                  .out(dut3_out), .pc_out(dut3_pc), .halted(dut3_halted),
                                  .uart_tx(dut3_tx));

  task automatic check8(input logic [7:0] got, input logic [7:0] exp,
                          input string label);
    begin
      if (got !== exp) begin
        $display("FAIL [%s] got 0x%02h, expected 0x%02h", label, got, exp);
        errors = errors + 1;
      end
    end
  endtask

  // ---- main ------------------------------------------------------------

  initial begin
    $dumpfile("tb.vcd");
    $dumpvars(0, tb);

    // ---- Test 1: Fibonacci ----
    do_reset();
    begin
      int cycles; cycles = 0;
      while (!dut1_halted && cycles < 1000) begin
        @(posedge clk); cycles = cycles + 1;
      end
      if (!dut1_halted) begin
        $display("FAIL [fib] did not halt within 1000 cycles");
        errors = errors + 1;
      end
    end
    // Expected regfile after Fibonacci program completes:
    //   R1=1, R2=1, R3=2, R4=3, R5=5, R6=8, R7=8 (= R6 → out)
    check8(dut1.regs[1], 8'd1, "fib R1");
    check8(dut1.regs[2], 8'd1, "fib R2");
    check8(dut1.regs[3], 8'd2, "fib R3");
    check8(dut1.regs[4], 8'd3, "fib R4");
    check8(dut1.regs[5], 8'd5, "fib R5");
    check8(dut1.regs[6], 8'd8, "fib R6");
    check8(dut1_out,     8'd8, "fib out (R7)");

    // ---- Test 2: countdown loop with CMP + BNZ ----
    do_reset();
    begin
      int cycles; cycles = 0;
      while (!dut2_halted && cycles < 1000) begin
        @(posedge clk); cycles = cycles + 1;
      end
      if (!dut2_halted) begin
        $display("FAIL [loop] did not halt within 1000 cycles");
        errors = errors + 1;
      end
    end
    // R1 should have decremented to 0; R2 should have tallied 5 iterations.
    check8(dut2.regs[1], 8'd0, "loop R1 final");
    check8(dut2.regs[2], 8'd5, "loop R2 tally");
    check8(dut2_out,     8'd5, "loop out (R7=R2)");

    // ---- Test 3: JMP forward skips the AND ----
    do_reset();
    begin
      int cycles; cycles = 0;
      while (!dut3_halted && cycles < 1000) begin
        @(posedge clk); cycles = cycles + 1;
      end
      if (!dut3_halted) begin
        $display("FAIL [jmp] did not halt within 1000 cycles");
        errors = errors + 1;
      end
    end
    check8(dut3.regs[3], 8'hFF, "jmp R3 (= OR result, AND skipped)");
    check8(dut3_out,     8'hFF, "jmp out (R7=R3)");

    if (errors == 0) $display("PASS: tiny FSM CPU, all programs executed correctly.");
    else             $display("FAIL: %0d errors", errors);

    $finish;
  end

  initial begin
    #5_000_000;
    $display("FAIL: testbench timed out");
    $finish;
  end

endmodule

`default_nettype wire