P37 keeps the P36 RV32IM platform and closes the first two extension gaps from
the compliance sweep: Zicsr and Zifencei.
Status: hardened. LibreLane run
RUN_2026-05-02_22-49-46produced a final GDS and passed Magic DRC, KLayout DRC, LVS, antenna, routing DRC, setup timing, hold timing, and max fanout in the recorded metrics. The flow’s max-slew and max-cap checkers passed, but the slow-corner (max_ss_100C_1v60) recorded83slew and8cap warnings on the new CSR datapath - a partial regression of the P36 DRV win.
The Result
Run it:
make -C projects/37_rv32im_zicsr_zifencei/test clean allResult: PASS
| check | result |
|---|---|
Build linked rv32im_zicsr runtime ELF | PASS |
| UART-load compiled image | PASS |
Execute C *, /, and % through RV32M | PASS |
Execute mulh, mulhsu, and mulhu | PASS |
| Check divide-by-zero and overflow edge cases | PASS |
MMIO UART writes M, T, E | PASS |
| MMIO timer interrupt visible to C | PASS |
| External interrupt visible to C | PASS |
Halt with x5 = 1 | PASS |
ACT4/Sail rv32i/I: PASS=39 FAIL=0 NOT RUN=0
ACT4/Sail rv32i/M: PASS=8 FAIL=0 NOT RUN=0
ACT4/Sail rv32i/Zicsr: PASS=6 FAIL=0 NOT RUN=0
ACT4/Sail rv32i/Zifencei: PASS=1 FAIL=0 NOT RUN=0
Full RISC-V compliance: PARTIAL
Harden Result
LibreLane flow: PASS
| harden check | result |
|---|---|
| Run directory | projects/37_rv32im_zicsr_zifencei/librelane/runs/RUN_2026-05-02_22-49-46 |
| Final GDS | projects/37_rv32im_zicsr_zifencei/librelane/runs/RUN_2026-05-02_22-49-46/final/gds/top.gds |
| Metrics | projects/37_rv32im_zicsr_zifencei/librelane/runs/RUN_2026-05-02_22-49-46/final/metrics.json |
| Magic DRC | PASS (0 errors) |
| KLayout DRC | PASS (0 errors) |
| LVS | PASS (0 errors) |
| Antenna | PASS (0 net violations, 0 pin violations) |
| Routing DRC | PASS (0 errors) |
| Magic/KLayout XOR | PASS (0 differences) |
| Setup timing | PASS (0 violations, worst setup slack 8.742 ns) |
| Hold timing | PASS (0 violations, worst hold slack 0.105 ns) |
| Max slew (flow checker) | PASS |
| Max cap (flow checker) | PASS |
| Max fanout | PASS (0 violations against signoff limit 13) |
The flow checkers passed, but the recorded slow-corner metrics show a partial
DRV regression vs P36. max_ss_100C_1v60 came back with 83 max-slew and 8
max-cap warnings. Every other corner stayed at 0.
P35 -> P36 -> P37 backend comparison:
| metric | P35 | P36 | P37 |
|---|---|---|---|
| Worst setup slack | 8.048 ns | 5.903 ns | 8.742 ns |
| Worst hold slack | 0.100 ns | 0.070 ns | 0.105 ns |
Max slew vio (max_ss) | 13 | 0 | 83 |
Max cap vio (max_ss) | 1 | 0 | 8 |
| Max fanout vio | 0 | 0 | 0 |
| Standard-cell area | 188652 um^2 | 191659 um^2 | 191927 um^2 |
| Standard-cell count | 26883 | 27223 | 27157 |
The new logic is small in cells but adds a writable mscratch register and
new CSR-readout muxes that participate in the existing CSR datapath. That is
where the new slow-corner slew/cap warnings live. The honest read is that the
P36 DRV win was sensitive to the exact CSR datapath shape and recovered
partially when that shape changed. Setup and hold both improved relative to
P36, so timing is not the pressure point.
What Changed
P37 adds writable mscratch at CSR address 0x340. The existing CSR execution
path already knew how to perform csrrw, csrrs, csrrc, and the immediate
forms; it needed a writable architectural CSR that the official tests could
use without tripping illegal-instruction handling.
P37 also makes fence.i legal. In this core there is no instruction cache and
no hidden prefetch queue, so fence.i is a no-op for hardware state. The
important part is that decode now recognizes it as a real instruction instead
of treating it as illegal.
misa still reports RV32IM (0x40001100). That is intentional because
Zicsr and Zifencei do not have their own single-letter misa bits.
Scope
| instruction family | status |
|---|---|
| RV32I base integer instructions | PASS in scoped ACT4/Sail rv32i/I |
MUL, MULH, MULHSU, MULHU | PASS in scoped ACT4/Sail rv32i/M |
DIV, DIVU, REM, REMU | PASS in scoped ACT4/Sail rv32i/M |
csrrw, csrrs, csrrc | PASS in scoped ACT4/Sail rv32i/Zicsr |
csrrwi, csrrsi, csrrci | PASS in scoped ACT4/Sail rv32i/Zicsr |
fence.i | PASS in scoped ACT4/Sail rv32i/Zifencei |
Still unsupported or NOT RUN: atomics, compressed instructions, floating
point, bitmanip, cache-block operations, supervisor mode, vectored mtvec,
delegation CSRs, satp, PMP, an MMU, and official full compliance packaging.
What We Learned
The P36 failures were real but narrow. We did not need a new runtime, a new bus,
or a larger memory system to pass the first CSR and instruction-fence extension
batches. We needed mscratch and a deliberate fence.i answer.
That turns P37 into a clean architectural checkpoint: RV32I, RV32M, Zicsr, and Zifencei all pass the scoped ACT4/Sail batches we have wired into the repo. The next useful RISC-V work should expand the official-test surface rather than keep poking at the already-green I/M/CSR/fence lane.