librelane playground

No. 48 / project of 147 on the ladder

Trap delegation CSR scaffolding

introduces — medeleg/mideleg as M-readable storage; staging for the M↔S priv transition rung

harden statelast run2026-05-03
areaunknownμm²
signoff
  • DRCNOT RUN
  • LVSNOT RUN
  • antennaNOT RUN
artifacts

P48 adds the trap-delegation CSRs - medeleg and mideleg - as M-mode-readable storage. Same scaffold-then-behavior pattern as P47.

Status: RTL pass. Probe extension (two more sub-checks) all PASS at 5,101,647 clocks. FreeRTOS demo still PASSES afterwards.

What it does

medeleg (0x302) and mideleg (0x303) are how M mode tells the hardware which exception causes / interrupt sources should be delegated to S mode (i.e. trap directly to S without bouncing through M). Linux writes both very early in boot - page faults, ecall-from-U, and the supervisor timer/external interrupts get delegated so the kernel can handle them without a redundant M-mode hop.

In P48 the chip stores the bits but does not actually delegate anything. Trap entry still routes everything to M-mode. The two behaviors are separable, so we land the address map first.

What changed

One file, ~25 lines of RTL:

  • New localparams CSR_MEDELEG, CSR_MIDELEG.
  • Two 32-bit storage flops.
  • Entries in csr_known, csr_writable, csr_read(), reset block, and the S_EXECUTE write switch.

Probe writes 0xDEADC001 -> medeleg, 0xDEADC002 -> mideleg, reads each back. Error codes 90-91.

Files

  • src/top.sv - medeleg/mideleg as M-readable storage
  • app/main.c - probe extended with two more sub-checks

Harden

NOT RUN. Estimated +75 cells over P47 (two 32-bit registers plus decode/mux).

What just happened?

Trap-delegation addresses are now decoded and round-tripping. The chip is still M-mode-only with no actual delegation behavior; the next rung is the priv-mode FSM that wires medeleg/mideleg, mstatus.MPP, and mret together to take the chip into S mode for the first time.