librelane playground

No. 56 / project of 147 on the ladder

RTL completion for Linux boot

introduces — hardware A/D bit updates in the Sv32 walker; CLINT-shaped timer at SiFive-standard MMIO addresses

harden statelast run2026-05-03
areaunknownμm²
signoff
  • DRCNOT RUN
  • LVSNOT RUN
  • antennaNOT RUN
artifacts

P56 closes the last two RTL holes that block actual Linux boot:

  1. Hardware A/D bit updates. Linux PTEs start with A=0/D=0 and rely on hardware to set them on first access. P52-P55 trapped; P56 writes the PTE back with the bit set and proceeds.
  2. CLINT-shaped timer aliases. SiFive-standard addresses for mtime (0x0200_BFF8) and mtimecmp (0x0200_4000) route to the existing timer registers, so a stock Linux DTS naming those addresses finds the right hardware.

Status: RTL pass. ad_update_probe + all P52-P55 probes PASS at 5,394,570 clocks. FreeRTOS demo continues running.

What changed

  • Two new walker states (S_PTW0_AD, S_PTW1_AD) that write the updated PTE back at the same address it was read from.
  • ptw_pte_ad_q register stashes the modified PTE between read and write-back.
  • Permission check restructured: faults only on permanent permission failures (R=0/W=0); A/D issues route through the AD update path.
  • cpu_mmio_sel recognises both 0x10xx_xxxx (legacy) and 0x02xx_xxxx (CLINT) ranges; address decode aliases mtime and mtimecmp to the SiFive-standard offsets.

What’s tested

ad_update_probe:

  • Plant a 4 KiB-page mapping with A=0/D=0.
  • mret to S, load via VA — verify no fault, PTE.A is now set, PTE.D still 0.
  • Re-plant A=1/D=0, store via VA — verify PTE.D is now set, store data was written.

All earlier probes still pass.

What’s left for actual Linux boot

The chip’s RTL is essentially complete. Remaining work is content:

  • Real Linux RV32 kernel image (build with our toolchain).
  • Real SBI v0.1+ runtime (full early-boot function set).
  • Hand-written DTB describing the platform.
  • Microscopic initramfs.
  • Instruction fetch translation (deferred — Linux can identity-map its own kernel; user-mode programs need it).

These are integration / supervised work. P57+ tackles them.

Files

  • src/top.sv - A/D update walker + CLINT aliases
  • app/main.c - ad_update_probe

Harden

NOT RUN. ~50 cells over P55.

What just happened?

The chip’s RTL is now Linux-ready. The walker hardware-updates A/D bits, the timer is at SiFive-standard addresses, the priv machinery and Sv32 paging all work. From here it’s a matter of building the kernel + firmware + DTB and seeing what breaks.