ACT4 generates RV32I/I ELFs that P17 can run

Today we checked the gap between P25 and a real current riscv-arch-test flow.

The old riscof path is not the current thing here. The upstream riscv-arch-test repo now uses ACT4: it builds reference signatures with Sail, then emits self-checking ELFs for the DUT.

Temporary setup:

cd /tmp/riscv-arch-test
PATH=/tmp/sail-riscv-0.10/bin:$PATH \
  mise exec -- uv run act /tmp/act-p17-check/test_config.yaml \
    --test-dir tests \
    --workdir /tmp/act-check-p17halt \
    --extensions I \
    --exclude '' \
    --jobs 8 \
    --fast

Result: PASS

ACT4 build summary: Build complete: 156 succeeded

That produced 39 final self-checking ELFs under /tmp/act-check-p17halt/sail-RVI20U32/elfs/rv32i/I.

Then we converted each ELF with riscv64-elf-objcopy -O verilog and UART-loaded it into the existing P17 simulator.

Result: PASS

Summary: PASS=39 FAIL=0 NOT RUN=0

This is stronger than P25’s first result because the expected signatures came from ACT4 plus Sail, not from the local Python reference path.

It is still not a full RISC-V compliance claim. The temporary config uses a P17-specific low-memory Sail map and a bilingual halt macro: write tohost for Sail, then set x5 and execute jal x0, 0 for the P17 testbench. We also only ran the rv32i/I directory. No privileged tests, trap tests, CSR tests, or extension tests are claimed.

The honest new claim is:

P17/P25 can run all 39 ACT4-generated, Sail-backed, self-checking rv32i/I ELFs through the UART external-memory harness.