RV32I/I official test set

P25 adds the official load and store tests to the P24 strict subset.

Status: RTL pass for all 39 local official rv32i/I tests. These are upstream riscv-arch-test sources built in RVTEST_SELFCHECK mode, UART-loaded into the P17 external-memory model, and accepted only when the core reaches the local pass convention.

The Result

Run it:

make -C projects/25_rv32i_full_i_tests/test

Summary: PASS=39 FAIL=0 NOT RUN=0

This is not a full RISC-V compliance claim. It is a precise claim for the local official rv32i/I test directory.

ACT4 Probe

We also checked the current upstream ACT4 flow against the same core harness. ACT4 used Sail to generate expected signatures, then produced final self-checking ELFs. Those ELFs were converted to Verilog memory images and UART-loaded into the P17 external-memory simulator.

Result: PASS

Summary: PASS=39 FAIL=0 NOT RUN=0

This is still scoped to rv32i/I. It is not a full compliance claim, but it does remove the biggest caveat from the first P25 run: the expected signatures were generated by ACT4 plus Sail rather than by our local Python reference path.

Signature Model

The load/store tests use the reference-emulated signature flow:

1. Build the official test in normal signature-writing mode.
2. Run that image through the local RV32I interpreter.
3. Read the signature words.
4. Rebuild the test in RVTEST_SELFCHECK mode with those words.

For P25, that path covers jumps, branches, loads, and stores.

What This Proves

The core passes the local official RV32I base-integer instruction tests in the current harness: ALU operations, upper immediates, direct and indirect jumps, branches, loads, and stores.

The next honest step is not to say “done.” It is to harden this exact tested core configuration, then decide whether the next expansion is broader architecture-test coverage, Tiny Tapeout packaging, or extra implementation features such as traps and CSRs.