P26 makes the ACT4 probe repeatable

P26 is not new silicon. It is the day we stopped letting the strongest compliance-adjacent result live in /tmp.

The new command is:

make -C projects/26_rv32i_act4_probe/test

It runs upstream ACT4, lets Sail generate the expected signatures, converts the final self-checking ELFs to Verilog memory images, and UART-loads each one into the P17 external-memory simulator.

Result: PASS

Summary: PASS=39 FAIL=0 NOT RUN=0

The awkward part was the stop convention. Sail wants tohost; the P17 testbench wants x5 plus a self-loop. The checked-in ACT4 macro now writes tohost, sets x5, and then executes jal x0, 0.

The other adaptation is address zero. P17 boots at 0x00000000, while the stock Sail config assumes RAM at 0x80000000. The runner patches a temporary Sail JSON memory map for low executable RAM before invoking ACT4.

This does not make the core “RISC-V compliant.” It makes the claim much cleaner:

ACT4-generated, Sail-backed, self-checking rv32i/I ELFs pass through the current P17/P25 harness.

Next useful RISC-V work: stop expanding the base integer instruction list and start building the machine-mode substrate: mstatus, mtvec, mepc, mcause, mtval, mret, ecall, ebreak, illegal-instruction traps, and timer/interrupt plumbing. That is the path from “passes instruction tests” to “can host real runtime software.”