librelane playground

No. 26 / project of 147 on the ladder

RV32I ACT4 probe

introduces — Reproducible ACT4 plus Sail run for the full rv32i/I test directory

harden statelast run2026-05-01
signoff
  • DRCNOT RUN
  • LVSNOT RUN
  • antennaNOT RUN
artifacts

P26 turns the ACT4 experiment into a repeatable project command. It does not add new CPU RTL; it makes the current upstream architecture-test flow reproducible against the P17/P25 core harness.

Status: RTL pass for all 39 ACT4-generated, Sail-backed rv32i/I self-checking ELFs. The ELFs are UART-loaded through the P17 external-memory simulator. This is not a full RISC-V compliance claim.

The Result

Run it:

make -C projects/26_rv32i_act4_probe/test

Result: PASS

Summary: PASS=39 FAIL=0 NOT RUN=0

The result table is written to:

  • projects/26_rv32i_act4_probe/results/RESULTS.md
  • projects/26_rv32i_act4_probe/results/act4_rv32i_I.csv

What ACT4 Does

ACT4 is the current upstream riscv-arch-test flow. For this probe it:

  1. Compiles the official rv32i/I sources.
  2. Runs Sail to generate reference signatures.
  3. Builds final self-checking DUT ELFs.
  4. Leaves those ELFs under the ACT4 work directory.

P26 then converts each ELF to a Verilog memory image and runs the existing P17 UART-loader simulator.

The Local Adaptation

Sail and P17 do not use the same stop signal. Sail watches tohost; the P17 testbench watches x5 and a jal x0, 0 halt loop.

P26 uses a small DUT macro file that does both:

write tohost
set x5 to the local PASS or FAIL code
jal x0, 0

The linker script also places the image at 0x00000000, because P17 boots at zero. During the run, the script patches the temporary Sail memory map so low memory is executable and writable.

What This Proves

This is stronger than P25’s local reference path: the expected signatures come from ACT4 plus Sail.

The honest claim is still scoped:

P17/P25 can run all 39 ACT4-generated, Sail-backed, self-checking rv32i/I ELFs through the UART external-memory harness.

Not covered: traps, exceptions, CSRs, privilege modes, misalignment behavior, FENCE.I, multiply/divide, atomics, compressed instructions, or a complete official report package for a named RISC-V profile.