journal 2026-05-01

P33 closes RV32IM setup timing

p33riscvrv32mtimingharden

P33 is the timing cleanup pass for P32.

P32 had a credible 32-cycle divider, but multiply and high-half multiply were still wide combinational product paths. The P32 harden run completed physical signoff, but setup timing failed: worst setup slack was -7.798 ns with 474 setup violations.

The fix was to make MUL, MULH, MULHSU, and MULHU iterative. The core now enters S_MUL, runs a 32-cycle shift/add multiply, then writes back either the low or high product word. Divide/remainder stay on the 32-cycle restoring divider from P32.

Commands:

make -C projects/33_rv32im_timing_fix/test clean all
make -C projects/33_rv32im_timing_fix/test act4
make -C projects/33_rv32im_timing_fix/test act4_m
make harden PROJECT=33_rv32im_timing_fix

Results:

checkresult
Compiled RV32IM runtimePASS
ACT4/Sail rv32i/IPASS=39 FAIL=0 NOT RUN=0
ACT4/Sail rv32i/MPASS=8 FAIL=0 NOT RUN=0
LibreLane flowPASS
Magic DRCPASS
KLayout DRCPASS
LVSPASS
AntennaPASS
Setup timingPASS, worst setup slack 4.031 ns
Hold timingPASS, worst hold slack 0.110 ns
Max slewFAIL, 2241 violations
Max capFAIL, 291 violations
Full RISC-V complianceNOT RUN

Final artifacts:

artifactpath
Run directoryprojects/33_rv32im_timing_fix/librelane/runs/RUN_2026-05-01_13-44-20
Final GDSprojects/33_rv32im_timing_fix/librelane/runs/RUN_2026-05-01_13-44-20/final/gds/top.gds
Metricsprojects/33_rv32im_timing_fix/librelane/runs/RUN_2026-05-01_13-44-20/final/metrics.json

There were two harden runs. The first P33 run proved the RTL change fixed setup: setup violations dropped to 0, but the default 0.75 ns transition constraint left 5824 max-slew and 88 max-cap violations. The second run used the sky130-realistic MAX_TRANSITION_CONSTRAINT: 1.5 and stronger repair margins. That improved max slew to 2241, but max cap rose to 291.

The practical result: the architectural timing problem is fixed, but electrical DRV cleanup remains. The next useful pass should look at reset/load-mode fanout and backend repair choices instead of adding more ISA features.