librelane playground

No. 33 / project of 147 on the ladder

RV32IM timing fix

introduces — Iterative RV32M multiply, setup timing closure, and realistic transition repair

harden statelast run2026-05-01
cells25,901non-filler
slack4.03ns setup
area900 x 900 die, 190613 stdcell areaμm²
signoff
  • DRCPASS
  • LVSPASS
  • antennaPASS
artifacts

P33 keeps the P32 RV32IM platform and fixes the setup timing failure by making multiply multi-cycle. P32 already moved divide/remainder out of the single-cycle path; P33 does the same kind of thing for MUL, MULH, MULHSU, and MULHU.

Status: hardened, with residual electrical DRV cleanup left. LibreLane run RUN_2026-05-01_13-44-20 produced final GDS and passed Magic DRC, KLayout DRC, LVS, antenna, setup timing, and hold timing. Max slew and max cap still report violations, so this is not a perfectly clean electrical checkpoint.

The Result

Run it:

make -C projects/33_rv32im_timing_fix/test clean all

Result: PASS

checkresult
Build linked rv32im_zicsr runtime ELFPASS
UART-load compiled imagePASS
Execute C *, /, and % through RV32MPASS
Execute mulh, mulhsu, and mulhuPASS
Check divide-by-zero and overflow edge casesPASS
MMIO UART writes M, T, EPASS
MMIO timer interrupt visible to CPASS
External interrupt visible to CPASS
Halt with x5 = 1PASS

ACT4/Sail rv32i/I: PASS=39 FAIL=0 NOT RUN=0

ACT4/Sail rv32i/M: PASS=8 FAIL=0 NOT RUN=0

Harden Result

LibreLane flow: PASS

harden checkresult
Run directoryprojects/33_rv32im_timing_fix/librelane/runs/RUN_2026-05-01_13-44-20
Final GDSprojects/33_rv32im_timing_fix/librelane/runs/RUN_2026-05-01_13-44-20/final/gds/top.gds
Metricsprojects/33_rv32im_timing_fix/librelane/runs/RUN_2026-05-01_13-44-20/final/metrics.json
Magic DRCPASS (0 errors)
KLayout DRCPASS (0 errors)
LVSPASS (0 errors)
AntennaPASS (0 violations)
Setup timingPASS (0 violations, worst setup slack 4.031 ns)
Hold timingPASS (0 violations, worst hold slack 0.110 ns)
Max slewFAIL (2241 violations, only slow corners)
Max capFAIL (291 violations)

For comparison, P32 hardened with worst setup slack -7.798 ns and 474 setup violations. P33 closes setup at the same 40 ns clock target.

What Changed

The supported instruction set did not expand; the implementation changed:

instructionP33 implementation
MUL32-cycle shift/add, low 32 bits
MULH32-cycle shift/add, high signed x signed word
MULHSU32-cycle shift/add, high signed x unsigned word
MULHU32-cycle shift/add, high unsigned x unsigned word
DIV, DIVU32-cycle restoring divider
REM, REMU32-cycle restoring divider remainder

RISC-V edge cases are included: divide by zero, signed overflow on 0x80000000 / -1, and the corresponding remainder behavior.

misa still reports IM: 0x40001100.

Runtime Shape

The runtime is the same RV32IM probe shape from P32. Ordinary C operators force mul, div, divu, rem, and remu into the compiler output. Inline assembly covers mulh, mulhsu, and mulhu, because C has no direct 32-bit high-product operator.

The generated runtime binary is 888 bytes in the current build.

Scope

This is not a full RISC-V compliance claim. The recorded official-test coverage is the scoped ACT4/Sail rv32i/I and rv32i/M batches listed above.

Still unsupported: atomics, compressed instructions, supervisor mode, vectored mtvec, delegation CSRs, satp, an MMU, and official full compliance packaging.