P36 gave us a clean target list: the RV32I and RV32M batches passed, while all
six Zicsr tests and the lone Zifencei test failed.
P37 keeps the same RV32IM platform and fixes those exact holes:
| suite | result |
|---|---|
ACT4/Sail rv32i/I | PASS=39 FAIL=0 NOT RUN=0 |
ACT4/Sail rv32i/M | PASS=8 FAIL=0 NOT RUN=0 |
ACT4/Sail rv32i/Zicsr | PASS=6 FAIL=0 NOT RUN=0 |
ACT4/Sail rv32i/Zifencei | PASS=1 FAIL=0 NOT RUN=0 |
| Full RISC-V compliance | PARTIAL |
The fix is deliberately boring. mscratch is now a writable machine-mode CSR,
so the CSR tests have a real architectural register to hammer with csrrw,
csrrs, csrrc, and their immediate forms. fence.i is legal as a no-op
because there is no instruction cache or prefetch queue in this external-memory
model.
This is not a full compliance claim. It is a better scoped official-test claim: the ladder now has RV32I, RV32M, Zicsr, and Zifencei passing under the ACT4/Sail harness. The next gap should come from expanding coverage, not reworking these four green suites.
Harden run
LibreLane run RUN_2026-05-02_22-49-46 produced a final GDS with clean Magic
DRC, KLayout DRC, LVS, antenna, routing DRC, setup, hold, and fanout. The
flow’s max-slew and max-cap checkers also passed. The slow-corner
(max_ss_100C_1v60) recorded metrics tell a more honest story:
metric (max_ss_100C_1v60) | P35 | P36 | P37 |
|---|---|---|---|
| Max slew violations | 13 | 0 | 83 |
| Max cap violations | 1 | 0 | 8 |
| Max fanout violations | 0 | 0 | 0 |
So the P36 backend win partially regressed when the new CSR readout/storage
joined the datapath. Setup slack actually improved (5.903 ns -> 8.742 ns)
and DRC/LVS are clean, so the GDS is real - the slow-corner DRV tail is the
piece that did not stay won. That is the kind of result the journal exists
for: a small architectural fix can quietly disturb a backend tail an earlier
rung had already beaten back.