librelane playground

No. 34 / project of 147 on the ladder

RV32IM DRV cleanup

introduces — Reset-tree cleanup, post-route repair, and DRV reduction

harden statelast run2026-05-01
cells27,147non-filler
slack7.47ns setup
area900 x 900 die, 192919 stdcell areaμm²
signoff
  • DRCPASS
  • LVSPASS
  • antennaPASS
artifacts

P34 keeps the P33 RV32IM platform and works on the electrical warnings left after timing closure. The ISA support does not change. The physical implementation does: the CPU run/reset release is registered, the core reset tree is made synchronous, and the LibreLane repair settings are pushed harder at the slow corner and after global routing.

Status: hardened, with a small DRV tail left. LibreLane run RUN_2026-05-01_14-58-10 produced final GDS and passed Magic DRC, KLayout DRC, LVS, antenna, setup timing, and hold timing. Max slew, max cap, and max fanout still report violations.

The Result

Run it:

make -C projects/34_rv32im_drv_cleanup/test clean all

Result: PASS

checkresult
Build linked rv32im_zicsr runtime ELFPASS
UART-load compiled imagePASS
Execute C *, /, and % through RV32MPASS
Execute mulh, mulhsu, and mulhuPASS
Check divide-by-zero and overflow edge casesPASS
MMIO UART writes M, T, EPASS
MMIO timer interrupt visible to CPASS
External interrupt visible to CPASS
Halt with x5 = 1PASS

ACT4/Sail rv32i/I: PASS=39 FAIL=0 NOT RUN=0

ACT4/Sail rv32i/M: PASS=8 FAIL=0 NOT RUN=0

Harden Result

LibreLane flow: PASS

harden checkresult
Run directoryprojects/34_rv32im_drv_cleanup/librelane/runs/RUN_2026-05-01_14-58-10
Final GDSprojects/34_rv32im_drv_cleanup/librelane/runs/RUN_2026-05-01_14-58-10/final/gds/top.gds
Metricsprojects/34_rv32im_drv_cleanup/librelane/runs/RUN_2026-05-01_14-58-10/final/metrics.json
Magic DRCPASS (0 errors)
KLayout DRCPASS (0 errors)
LVSPASS (0 errors)
AntennaPASS (0 violations)
Setup timingPASS (0 violations, worst setup slack 7.475 ns)
Hold timingPASS (0 violations, worst hold slack 0.106 ns)
Max slewFAIL (12 violations, all in max_ss_100C_1v60)
Max capFAIL (3 violations)
Max fanoutFAIL (9 violations)

The comparison to P33 is the point:

metricP33P34
Worst setup slack4.031 ns7.475 ns
Max slew violations224112
Max cap violations2913
Max fanout violations179
Standard-cell area190613 um^2192919 um^2
Standard-cell count2590127147

What Changed

The supported instruction set is the same as P33:

instruction familystatus
RV32I base integer instructionsPASS in scoped ACT4/Sail rv32i/I
MUL, MULH, MULHSU, MULHUPASS in scoped ACT4/Sail rv32i/M
DIV, DIVU, REM, REMUPASS in scoped ACT4/Sail rv32i/M
Zicsr machine-mode CSR subsetused by the runtime, not full CSR compliance

The implementation changes are physical-design oriented. The loader now releases the CPU through a registered cpu_run_q, and the main core reset is synchronous inside the CPU. The harden config also enables post-global-route design repair, post-global-route timing repair, stronger slew/cap margins, and 250 um wire repair.

Scope

This is not a full RISC-V compliance claim. The recorded official-test coverage is the scoped ACT4/Sail rv32i/I and rv32i/M batches listed above.

Still unsupported: atomics, compressed instructions, supervisor mode, vectored mtvec, delegation CSRs, satp, an MMU, and official full compliance packaging.