P35 is the follow-up to P34’s “small DRV tail” result. It keeps the same RV32IM platform and does not add new instructions. The work here is narrower: make the remaining high-fanout and slow-corner cones less silly, rerun the ACT4 coverage, and harden again with a practical LibreLane config.
Status: hardened, with residual DRV warnings. LibreLane run
RUN_2026-05-01_19-57-20produced final GDS and passed Magic DRC, KLayout DRC, LVS, antenna, routing DRC, setup timing, hold timing, and max fanout. Max slew and max cap still report a small slow-corner tail.
The Result
Run it:
make -C projects/35_rv32im_signoff_clean/test clean allResult: PASS
| check | result |
|---|---|
Build linked rv32im_zicsr runtime ELF | PASS |
| UART-load compiled image | PASS |
Execute C *, /, and % through RV32M | PASS |
Execute mulh, mulhsu, and mulhu | PASS |
| Check divide-by-zero and overflow edge cases | PASS |
MMIO UART writes M, T, E | PASS |
| MMIO timer interrupt visible to C | PASS |
| External interrupt visible to C | PASS |
Halt with x5 = 1 | PASS |
ACT4/Sail rv32i/I: PASS=39 FAIL=0 NOT RUN=0
ACT4/Sail rv32i/M: PASS=8 FAIL=0 NOT RUN=0
Full RISC-V compliance: NOT RUN
Harden Result
LibreLane flow: PASS
| harden check | result |
|---|---|
| Run directory | projects/35_rv32im_signoff_clean/librelane/runs/RUN_2026-05-01_19-57-20 |
| Final GDS | projects/35_rv32im_signoff_clean/librelane/runs/RUN_2026-05-01_19-57-20/final/gds/top.gds |
| Metrics | projects/35_rv32im_signoff_clean/librelane/runs/RUN_2026-05-01_19-57-20/final/metrics.json |
| Magic DRC | PASS (0 errors) |
| KLayout DRC | PASS (0 errors) |
| LVS | PASS (0 errors) |
| Antenna | PASS (0 net violations, 0 pin violations) |
| Routing DRC | PASS (0 errors) |
| Setup timing | PASS (0 violations, worst setup slack 8.048 ns) |
| Hold timing | PASS (0 violations, worst hold slack 0.100 ns) |
| Max slew | FAIL (13 violations, all in max_ss_100C_1v60) |
| Max cap | FAIL (1 violation) |
| Max fanout | PASS (0 violations) |
The comparison to P34 is the real story:
| metric | P34 | P35 |
|---|---|---|
| Worst setup slack | 7.475 ns | 8.048 ns |
| Worst hold slack | 0.106 ns | 0.100 ns |
| Max slew violations | 12 | 13 |
| Max cap violations | 3 | 1 |
| Max fanout violations | 9 | 0 |
| Standard-cell area | 192919 um^2 | 188652 um^2 |
| Standard-cell count | 27147 | 26883 |
What Changed
The supported instruction set is the same as P34:
| instruction family | status |
|---|---|
| RV32I base integer instructions | PASS in scoped ACT4/Sail rv32i/I |
MUL, MULH, MULHSU, MULHU | PASS in scoped ACT4/Sail rv32i/M |
DIV, DIVU, REM, REMU | PASS in scoped ACT4/Sail rv32i/M |
| Zicsr machine-mode CSR subset | used by the runtime, not full CSR compliance |
The implementation changes are mostly cleanup. mtvec is now a low-memory
WARL CSR: only bits [11:2] are stored, bits [31:12] read as zero, and the
core still uses direct trap mode only. That matches this tiny platform’s low
external RAM map and cuts down the CSR/trap cone.
The divider also selects quotient-versus-remainder before applying the final sign correction. That avoids keeping two parallel two’s-complement result paths alive at the final divider writeback.
Scope
This is not a full RISC-V compliance claim. The recorded official-test coverage
is the scoped ACT4/Sail rv32i/I and rv32i/M batches listed above.
Still unsupported: atomics, compressed instructions, supervisor mode, vectored
mtvec, delegation CSRs, satp, an MMU, and official full compliance
packaging.
What We Learned
P35 did not magically turn the chip into a perfect electrical-signoff example. It did clean up fanout completely and reduce cap to one violation, while keeping the ACT4 I/M coverage green and producing DRC/LVS/antenna-clean GDS.
The remaining slew tail is now a specific slow-corner datapath problem. That is better than broad reset-tree noise, but it is not worth turning this ladder rung into an open-ended backend tuning swamp.