P19 keeps the P17 hardened logic shell and P18 signature-debug approach, then widens the strict official-test target to cover the immediate ALU group.
Status: RTL pass for a 12-test official subset. These are upstream
riscv-arch-testsources built inRVTEST_SELFCHECKmode, UART-loaded into the P17 external-memory model, and accepted only when the core reaches the local pass convention.
The Result
Run it:
make -C projects/19_rv32i_imm_alu_tests/test| test | result |
|---|---|
I-nop-00.S | PASS |
I-fence-00.S | PASS |
I-lui-00.S | PASS |
I-addi-00.S | PASS |
I-ori-00.S | PASS |
I-andi-00.S | PASS |
I-xori-00.S | PASS |
I-slti-00.S | PASS |
I-sltiu-00.S | PASS |
I-slli-00.S | PASS |
I-srli-00.S | PASS |
I-srai-00.S | PASS |
This is not a full RV32I compliance claim. It is a larger, strict, official subset.
Signature Model
The batch runner now recognizes generated immediate-ALU test patterns:
RVTEST_TESTDATA_LOAD_INT(..., xN) # load rs1: xN = 0x...
op xD, xN, IMM # perform operationand computes expected signature words for ADDI, ORI, ANDI, XORI,
SLTI, SLTIU, SLLI, SRLI, and SRAI.
The honesty boundary is still explicit: tests without a generated signature model keep the placeholder signature and are not claimed by P19.
What This Proves
P19 moves the question from setup plumbing to instruction behavior. The UART loader, external memory path, and self-check harness are good enough to run a useful immediate-ALU official subset.
The next natural targets are AUIPC and the R-type ALU tests. Those will
either be more signature-model work or the first real core bug.