RV32I R-type ALU official subset · librelane-playground

P20 keeps the P17 hardened logic shell and the P18/P19 signature-generation flow, then widens the strict official-test target to cover the R-type ALU group.

Status: RTL pass for a 22-test official subset. These are upstream riscv-arch-test sources built in RVTEST_SELFCHECK mode, UART-loaded into the P17 external-memory model, and accepted only when the core reaches the local pass convention.

The Result

Run it:

make -C projects/20_rv32i_rtype_alu_tests/test

test	result
`I-nop-00.S`	`PASS`
`I-fence-00.S`	`PASS`
`I-lui-00.S`	`PASS`
`I-addi-00.S`	`PASS`
`I-ori-00.S`	`PASS`
`I-andi-00.S`	`PASS`
`I-xori-00.S`	`PASS`
`I-slti-00.S`	`PASS`
`I-sltiu-00.S`	`PASS`
`I-slli-00.S`	`PASS`
`I-srli-00.S`	`PASS`
`I-srai-00.S`	`PASS`
`I-add-00.S`	`PASS`
`I-sub-00.S`	`PASS`
`I-or-00.S`	`PASS`
`I-and-00.S`	`PASS`
`I-xor-00.S`	`PASS`
`I-sll-00.S`	`PASS`
`I-srl-00.S`	`PASS`
`I-sra-00.S`	`PASS`
`I-slt-00.S`	`PASS`
`I-sltu-00.S`	`PASS`

This is not a full RV32I compliance claim. It is a larger, strict, official subset.

Signature Model

The batch runner now recognizes generated R-type ALU test patterns:

RVTEST_TESTDATA_LOAD_INT(..., xN) # load rs1: xN = 0x...
RVTEST_TESTDATA_LOAD_INT(..., xM) # load rs2: xM = 0x...
op xD, xN, xM # perform operation

and computes expected signature words for ADD, SUB, OR, AND, XOR, SLL, SRL, SRA, SLT, and SLTU.

The honesty boundary is still explicit: tests without a generated signature model keep the placeholder signature and are not claimed by P20.

What This Proves

The official pass set now covers the no-op/fence baseline, LUI, all immediate ALU tests in this modeled subset, and all R-type ALU tests in this modeled subset.

That is still a small island inside RV32I, but it is a useful one. The next real work is control flow and addressing: AUIPC, JAL, JALR, branches, and load/store tests.